Announcements

1. Dr. Fourney's schedule for finals week.

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@sdstate.edu
Phone	688-4016
Office	215 Harding Hall
Class Time	MWF 12:00-1:50
Class Location	Crothers Engineering Hall, room 351
Office hours	MWF 10-11, Tu 12-1, Th 12:30-1:30 Please do not disturb MWF 7-8 or 11-12 Other times by available by appointment
Text	Digital Design: Principles & Practices 3rd Ed. by John F. Wakerly, published by Prentice Hall Companion Web Site: ddpp.com The text will be supplemented with additional reference materials which will be linked from this page and/or handed out in class as they are assigned.

Corequisites

EE 245L -- Digital Systems Lab

Course Description

This course serves as an introduction digital logic systems. After successfully completing this course, the students will be capable of understanding, designing, and building digital systems.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will be determined via the following breakdown:

 

Exam #1	20%
Exam #2	20%
Homework and Quizzes	10%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Project and PDR	15%
Comprehensive Final Exam	20%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.   Please read Making the Grade by Kurt Wiesenfeld and keep his views (which I share) in mind when deciding how much effort to invest in your coursework.

Schedule of Upcoming Classes

No. Date Topic, Reading, and Assignment 1 Sep 1 Introduction, go over Syllabus Skim Chapter 1 Homework # 1 assigned. 2 Sep 3 Introduced Positional Number systems, began addition and subtraction covered Chapter 2 - 2.4 Homework # 2 assigned. Sep 6 No Class -- Labor Day 3 Sep 8 Complete Section 2.4 -- addition and subtraction Representation of negative numbers - section 2.5 (except for 2.5.7) Addition and subtraction w/ negative numbers - section 2.6 and 2.7 We will eventually cover chapter 2 through section 2.13 (ending at the bottom of page 56), skipping sections 2.5.7, 2.8, and 2.9. 4 Sep 10 Finish Chapter 2 Homework 2 due before class, on the table in the front of the room Homework # 3 assigned. Due before class on Friday, 9/17 5 Sep 13 Finish Chapter 3. Digital abstraction. Logic circuit as black box. Truth Tables, logic gates (AND, OR, NOT, NAND, NOR) 6 Sep 15 Chapter 4. Boolean Algebra. Axioms and Theorems. 7 Sep 17 More on Theorems, consensus. HW 4 - 4.5, 4.6, 4.8 a, c, and h assigned. Due Monday 9/20) Homework 3 due before class. "Spiral" type paper will not be accepted 8 Sep 20 Terminology: literal, product term, sum term, minterm, maxterm, Canonical sum, canonical product, minterm list, maxterm list, etc. Deadline for 4.6 b and c extended till Noon on 9/22 9 Sep 22 Sum of products and product of sums implementation. Lots-O-algebra. Introduce Nand-Nand and Nor-Nor constructions. Covered Through section 4.2 Problems 4.6 b and c due before class. Homework #5 Problem 4.9, due Friday 10 Sep 24 Continue with Nand-Nand and Nor-Nor constructions, Circuit Synthesis, Circuit Manipulation/Minimization. Sections 4.3 - 4.3.7 Problem 4.13 assigned, due Wednesday 9/29 Problem 4.9 (HW 5) due before class. 11 Sep 27 Karnough Maps, prime implicant theorem, SOP and POS solutions, introduce concept of "don't care" entries in truth table and Karnough maps. Sections 4.3 - 4.3.7 Problem 4.19, 4.20, and 4.21, parts c-e assigned, due Friday 10/1 Problem 4.9 (HW 5) due before class. 12 Sep 29 Finish up POS and "don't care" conditions. (Sections 4.3.6-4.3.7) Begin Chapter 5 - Documentation Homework 8 assigned. due on Monday, October 4 Problem 4.13 due before class. 13 Oct 1 Chapter 5 - Documentation 13 Oct 1 Documentation, circuit timing (Sections 5-5.2) Problems 4.19, 4.20, 4.21 parts c-e due before class. 14 Oct 4 PLDs, PAL-devices and GALs Chapter 5-5.3.3, skip 5.3.4, 5.3.5. SKIM 5.3.6 Homework 8 Due before class 15 Oct 6 Decoders Sections 5.4-5.4.5 Skip 5.4.6-5.4.8 for now (we will probably have a lab based on 5.4.8 and will therefore cover 5.4.8 later). Oct 6 Optional evening help session. 5:00 pm in Crothers 351. Please bring questions, this is not a lecture. 16 Oct 8 First Exam Oct 11 No Class -- Native American Day 17 Oct 13 Discuss Exam, review decoders (and Lab 5) Introduce Encoders and priority encoders (Sections 5.5-5.5.2) 18 Oct 15 Homework 9 assigned. Due on 10/18. Priority encoders, three-state devices, multiplexers Sections 5.6-5.6.2 and 5.7-5.7.3 19 Oct 18 Ex-or gates: parity circuits, comparators, and adders Sections 5.8 through the second paragraph on page 415, 5.9-5.9.4, 5.10-5.10.2, skim 5.10.3-5.10.4, and lab material Skip Section 5.11 20 Oct 20 Combinational design example Sections 6-6.1 -- Barrel Shifter Example (skipped rest of Chapter 6) 21 Oct 22 Sequential Circuits. Bistable elements, S-R latches, D latches Homework 10 assigned. Due on Monday. 22 Oct 25 Introduce flip-flop. Distinguish from latch Homework #10 due before class 23 Oct 27 More w/ Flip Flops 24 Oct 29 Finite State Machine Analysis Chapter 7: Sections 7 -7.3 Exam will cover through today's lecture and homework 25 Nov 1 Finite State Machine Design: Sections 7.4-7.5 This material is not on Friday's exam, but will be needed to start your project ( which will be handed out at end of exam) 26 Nov 3 More design- unused states, design process, ambigious specifications, other design decisions Nov 3 Optional Review Session at 5:00 pm in CEH 305 27 Nov 5 Second Exam Project not assigned, but look at this 28 Nov 8 Discuss Exam Project discussed and assigned: Preliminary Design document due Nov 17th Be prepared to Demo by December 6th Final report due on December 10th 29 Nov 10 Another FSM design example, 3 bit counter with enable Nov 11 No Class -- Veteran's Day 30 Nov 12 HWK 11 assigned. Worked through string-detector example, design and implementation. 31 Nov 15 Went over (HW) solutions to 7.18 and 7.19. Discussed "multiple pop" problem with Mealy type inputs. Went over decomposition (breaking complicated machine into smaller, simpler sub-parts). Used Traffic light controller as an example. 32 Nov 17 Handout on this week's lab, discussion of 7-segment decoding and using either counters or T-type flip-flops to "divide" or slow down the system clock. Project Preliminary Design Document Due Homework 12 assigned. Due on Monday. 33 Nov 19 Quiz, discuss switch-bounce and potential cures, discuss HWK 12 with an example of a similar problem. 34 Nov 22 Discuss problems with PDRs. "magic" transistions, what happens when "don't cares" occur, getting extra pop, etc. 35 Nov 24 Project Discussion Nov 26 No Class -- Day after Thanksgiving 36 Nov 29 Project Q&A, introduce MSI counters. 37 Dec 1 Discuss MSI counters (Section 8.4 - 8.4.4) and shift registers (Section 8.5-8.5.3) Hints using counters for a quick and ugly debounce circuit, hints on using counters and decoders to time-multiplex your 7-segment displays. Discussed saving schematics as "symbols" for a hierarchial project. Optional reading: Here is a discussion of the more elegant debounce circuit that was mentioned in class. (From EDN). 39 Dec 6 Project Demos this week. Demo during, or prior to, your lab session this week OR seek prior permission to demo later. Discusssed projects, practicals, and static 1-hazards (Section 4.5-4.5.2) 40 Dec 8 More on documentation (Section 8-8.1.3, Skim 8.1.4) Sequential PLDs (Section 8.3 through page 687) Clock skew and asynchronous inputs (Sections 8.8) 41 Dec 10 Last Class Final Project Report Due If you do not have it ready by class time, you need to put it in my hands sometime Friday. Dec 14 Optional Review session at 5:00 PM in CEH 351 Dec 16 Final exam -- 2 pm -- Crothers 351 (Thursday, December 16)