Announcements

1. See the instructions below (Lecture 10, Sep 23) for accessing Prentice Hall's "onekey" system. Solutions to some of the problems in previous editions of your text can still be found at Dr. Wakerly's web site. Go all the way to the bottom and click on the link for his old page and then a link there for his old student site

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@sdstate.edu
Phone	688-4016
Office	215 Harding Hall
Class Time	MWF 12:00-12:50
Class Location	Crothers Hall, room 351
Office hours	To be determined the first full week of class
Text	Digital Design: Principles & Practices 4th Ed. by John F. Wakerly, published by Prentice Hall Companion Web Site: ddpp.com The text will be supplemented with additional reference materials which will be linked from this page and/or handed out in class as they are assigned.

Corequisites

EE 245L -- Digital Systems Lab

Course Description

This course serves as an introduction digital logic systems. After successfully completing this course, the students will be capable of understanding, designing, and building both combinational and sequential digital systems.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will probably be determined via the following breakdown:

 

Exam #1	20%
Exam #2	20%
Homework and Quizzes	10%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Project and PDR	15%
Comprehensive Final Exam	20%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.   Please read Making the Grade by Kurt Wiesenfeld and keep his views (which I share) in mind when deciding how much effort to invest in your coursework.

Schedule of Upcoming Classes

t Various clock issues -- Section 8.8-8.8.2 No. Date Topic, Reading, and Assignment 1 Aug 31 Introduction, go over Syllabus Skim Chapter 1 Homework # 1 assigned. 2 Sep 2 Introduce Positional Number systems and discuss first lab Chapter 2 - 2.4 Homework 2 assigned, due on Friday September 9th Lab handed out in class Sep 5 No Class -- Labor Day Holiday 3 Sep 7 Addition and subtraction --Section 2.4 Representation of negative numbers Section 2.5 except2.5.7 Homework # 2 assigned. 4 Sep 9 Addition and subtraction w/ negative numbers - section 2.6 and (with much less emphasis) 2.7 Binary Coded Decimal (first 5 paragraphs of Section 2.10 only) Gray Code --Section 2.11 We will eventually cover chapter 2 through section 2.13 (ending at the bottom of page 56), skipping sections 2.5.7, 2.8, and 2.9. Homework 2 due, Homework # 3 assigned. Due Monday 5 Sep 12 Finish Chapter 2 Briefly discuss ASCII - Section 2.12 Briefly discuss parity- Last paragraph on page 59 to Section 2.15.2 (including Table 2-13) Chapter 3. Digital abstraction. Logic circuit as black box. Truth Tables, logic gates, fan-out, delays (You should read sections 3-3.3.1, definition of "fan in" on page 92 (section 3.3.5), fan out (3.5.4), all of 3.5.7 (including the box on page 114) Discussion of Figure 3-36 on page 115, Fig 3-39 (118) and 3-41 (119). (This is ALL that we will cover in Chapter 3 for now) Homework 3 due before class, in the front of the room Homework # 4 assigned. Due Wednesday Read Chapter 4-4.3 before class on Wednesday 6 Sep 14 Chapter 4. Boolean Algebra. Axioms and Theorems. Homework # 5 assigned. Due on Friday 7 Sep 16 Duality, DeMorgan's theorem, literals, terms, minterms, and maxterms Homework # 6 assigned. Due on Monday 8 Sep 19 Continue with terminology: canonical sum, canonical product, minterm list, maxterm list, etc. Sum of products and product of sums implementation. Introduce Nand-Nand and Nor-Nor constructions. Through Section 4.2 Homework # 7 assigned. Due on Wednesday 9 Sep 21 More algebra. Introduce Karnough Maps, prime implicant theorem, SOP and POS solutions Sections 4.3 - 4.3.7 10 Sep 23 Finish up with SOP and POS solutions, introduce "don't care" conditions. (Sections 4.3.6-4.3.6 in your text, plus sections Min.1 and Min.2 on the one-key site). Homework # 8 assigned. Due on Monday Note: Consult your class notes from 9/21 before attempting to access OneKey. After that, go to the OneKeysite to register and/or login. Remember that all of the web designers at Prentice Hall failed "computer security 101" and any password you select will be stored in the clear on their machines and emailed back to you in cleartext. DO NOT "reuse" a password from another system. Once you gain access, you should start in the "Course Documents" section (this should happen automatically after you login) About 2/3 of the way down this page there is a hyperlink labeled "Min: Other Minimization Topics". Click that, then click the link for "Supplementary Section (PDF)". Then read sections Min.1 and Min.2. Their web server seems balky, in that I had to hit "reload" two or three times to get a valid PDF file. 11 Sep 26 Chapter 6 - 6.2 only (for now) - Introduction to Documentation and timing analysis Homework 8 due, optional Homework # 9 assigned. Due on Wednesday 12 Sep 28 Finished with 6.1 (documentation) and 6.2 (timing), then went into Chapter 5-5.1 Hardware Description Languages (Skip sections 5.2-5.3 as you read ahead) Homework # 10 assigned. Due on Friday 13 Sep 30 Continue with Chapter 5-5.1 Hardware Description Languages (Skip 5.2-5.3) Section 5.4-5.4.7 -- Basics of the Verilog Hardware Description language 14 Oct 3 PLDs, PAL-devices and GALs Oct 3 Optional Evening Review Session at 7:00 pm in Solberg 102 15 Oct 5 Exam #1 Homework # 11 assigned, Due Friday 16 Oct 7 MSI Components: Decoders Homework Due Homework # 12 assigned, Due Wednesday A note on the reading assignments For sections 6.4-6.9, we will cover all of the material on the MSI components, but skip the ABEL and VHDL sub-sections. The pattern will be to read until the topic switches to ABEL, skip the ABEL section, skip the VHDL section, then read the Verilog section. Oct 10 No Class. Native American Day 17 Oct 12 Encoders and Priority Encoders Homework # 13 assigned, Due Friday 18 Oct 14 Verilog discussion, verilog versions of several MSI components, pre-lab discussion. 19 Oct 17 More on three-state devices. Introduce and discuss multiplexers. Discuss Verilog implementation of three-states, transceivers, muxes. Homework # 14 and Homework # 15 assigned for Wednesday 20 Oct 19 Exclusive-or gates: parity circuits, comparators, adders, etc Homework # 16 assigned for Friday, and In addition to covering section 6.8 and 6.9 (skipping VHDL and ABEL subsections), you should: read section 6.10-6.10.2, then skim section 6.10.3-6.10.4, then read section 6.10.5, then skim section 6.10.6, and skip sections 6.10.7-6.10.9, then read section 6.10.10, then skip the remainder of Chapter 6. 21 Oct 21 Sequential Circuits. Stability and meta-stability, bistable elements, S-R latches Homework # 18 assigned, Due Monday, Mar 14 assigned -- due Monday Homework # 17 delayed until Wednesday 22 Oct 24 D latches, Introduce flip-flop (which is different from a latch!) Discussed D and J-K flip-flops. 23 Oct 26 Begin State Machines, analysis Chapter 7: Sections 7 -7.3 Homework # 19 assigned 24 Oct 28 Finite State Machine Design: Sections 7.4-7.5 Your project, which will be assigned soon, will be based on this topic Homework # 20 assigned 25 Oct 31 Another Finite State Machine Design Example -- sequence detector 26 Nov 2 Finite State Machine Design and Verilog Section 7.13-7.13.3 27 Nov 4 Go back over 7.13, everybody now understands how to generate their own Verilog code for a finite state machine in using the techniques that resulted in the code in Table 7-58 28 Nov 7 Using Verilog to implement an FSM without designing the actual state machine first. Nov 7 Optional review session at 7:00 PM in Solberg 102 29 Nov 9 Exam II Take a look at your project. The first deliverable is due next Wednesday (11/16), and you might want to get started on it this weekend. Nov 11 No Class -- Veteran's Day 30 Nov 14 Hand back and go over exam, discuss project, brief discussion of the problem caused by mealy type outputs changing late in the clock cycle and switch bounce. Here's some optional reading showing some emperical information on the duration of switch bounce. Homework # 21 assigned 31 Nov 16 Discuss pipelining mealy outputs (and why this isn't appropriate for your projects). Preliminary Design Document Due by 5 pm today 32 Nov 18 Counters. See also OneKey Section Cntr. Homework 21 due before class Homework # 22 assigned 33 Nov 21 Homework 22 due before class, hardcopy and softcopy by email Continue discussiong counters, and HW 22. Last minute discussion and preparation for lab practical 34 Nov 23 Decoding counter outputs in a glitch free manner, alternatives to debouncing the Digi I/O switches, shift registers and Johnson counters. Homework # 23 assigned Nov 25 No Class -- day after Thanksgiving Nov 28 No Class due to anticipated blizzard 35 Nov 30 Counter quiz, debounce discussion, Basic Verilog and timing review, based on lab observations. Homework 23 due 36 Dec 2 Sequential PLD discussion, Section BiPLD on OneKey and Section 8.3 in your text. 37 Dec 5 38 Dec 7 Finish up clock issues (Section 8.8.3) Dealing with asynchrnous inputs, design of synchronizers. Section 8.9-8.9.6 39 Dec 9 Memory -- ROM (PROM, EPROM, EEPROM, Flash) and RAM (DRAM,SRAM) CPLD and FPGA internals Assorted topics from Chapter 9 and lecture notes. Dec 14 Optional Review session at 6:00 PM in CEH 351 Dec 16 Final exam -- 2 pm -- Crothers 351 (Friday, Dec 16th)