Announcements

1. The pinout info for the Xilinx boards in lab.

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@ieee.org
Phone	Office 688-4016; Home number handed out in class
Office	215 Harding Hall
Class Time	MWF 11:00-11:50
Class Location	Crothers Hall, room 351
Office hours	MWF 3-4, Tu 12-1
Text	Digital Design: Principles & Practices 4th Ed. by John F. Wakerly, published by Prentice Hall There is a subscription based companion web site (so don't throw away the stuff that is packaged with your new book!). We will discuss how to access this site in class. A better, web resource can be found at: ddpp.com. This is the author's web site for an earlier version of the book. It is a much better web site, but (obviously) refers to a different (but similar) book. For example, you might find a problem solution to a problem in your book but the problem number will be different. You'll probably need to make use of both, since Prentice Hall saved some printing expense by putting some ``optional'' material on the web but not in the book. The text will be supplemented with additional reference materials which will be linked from this page and/or handed out in class as they are assigned.

Corequisites

EE 245L -- Digital Systems Lab

Course Description

This course serves as an introduction digital logic systems. After successfully completing this course, the students will be capable of understanding, designing, and building both combinational and sequential digital systems.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will probably be determined via the following breakdown:

 

Exam #1	20%
Exam #2	20%
Homework and Quizzes	10%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Project(s) and PDR(s)	15%
Comprehensive Final Exam	20%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.   Please read Making the Grade by Kurt Wiesenfeld and keep his views (which I share) in mind when deciding how much effort to invest in your coursework.

Schedule of Upcoming Classes

No. Date Topic, Reading, and Assignment 1 Aug 30 Introduction, go over Syllabus Skim Chapter 1 Homework # 1 assigned. 2 Sep 1 Introduce Positional Number systems and discuss first lab Chapter 2 - 2.4 Homework 2 assigned, due on Wednesday, September 6th Part A (of a 3 part lab) Lab was handed out in class. The other parts will be tutorials that you will step through, in lab, with the TA. The only thing you need to do prior to lab is complete the truth tables in the part handed out in class today. Sep 4 No Class, Labor Day -- don't forget about lab on Tuesday! 3 Sep 6 Addition and subtraction --Section 2.4 Representation of negative numbers Section 2.5 except2.5.7 Homework #2 Due before class Homework # 3 assigned. 4 Sep 8 Addition and subtraction w/ negative numbers - section 2.6 and (with much less emphasis) 2.7 Binary Coded Decimal (first 5 paragraphs of Section 2.10 only) Gray Code --Section 2.11 We will eventually cover chapter 2 through section 2.13 (ending at the bottom of page 56), skipping sections 2.5.7, 2.8, and 2.9. Homework # 4 assigned, due Monday. Homework 3 due, prior to the start of class Don't forget about the IEEE picnic tonight 5 Sep 11 Finish Chapter 2 Briefly discuss ASCII - Section 2.12 Briefly discuss parity- Last paragraph on page 59 to Section 2.15.2 (including Table 2-13) Chapter 3. Digital abstraction. Logic circuit as black box. Truth Tables, logic gates, fan-out, delays (You should read sections 3-3.3.1, definition of "fan in" on page 92 (section 3.3.5), fan out (3.5.4), all of 3.5.7 (including the box on page 114) Discussion of Figure 3-36 on page 115, Fig 3-39 (118) and 3-41 (119). (This is ALL that we will cover in Chapter 3 for now) Homework 4 due prior to the start of class. Read Chapter 4-4.3 before class on Wednesday 6 Sep 13 Chapter 4-4.1.3. Boolean Algebra, Axioms and Theorems. Read two lines on the "principle of duality" near the top of page 193 Homework # 5 assigned for Friday, you also now have enough background to complete Homework # 6 which is due on Monday. 7 Sep 15 Went over Algebra Homework More on Duality and DeMorgan's theorem. Homework 5 Due, don't forget about Homework # 6 which is Due on Monday 8 Sep 18 Discuss literals, terms, minterms, maxterms, canonical sum, canonical product, minterm list, maxterm list, etc. Homework 6 Due except for 4.9 9 Sep 20 Introduce Karnough Maps (Section 4.3.4) Prime implicant theorem, SOP and POS solutions, (Sections 4.3.4-4.3.6 in your text, plus section Min.1 on the one-key site). Homework # 7 assigned. Due on Monday Note: Consult your class notes from today before attempting to access OneKey. After that, go to the OneKeysite to register and/or login. Remember that all of the web designers at Prentice Hall failed "computer security 101" and any password you select will be stored in the clear on their machines and emailed back to you in cleartext. DO NOT "reuse" a password from another system. Once you gain access, you should start in the "Course Documents" section (this should happen automatically after you login) About 2/3 of the way down this page there is a hyperlink labeled "Min: Other Minimization Topics". Click that, then click the link for "Supplementary Section (PDF)". Then read sections Min.1 and Min.2. Their web server seems balky, in that I had to hit "reload" two or three times to get a valid PDF file. 10 Sep 22 More on K-maps, introduce "don't care" conditions (Wakerly 4.3.6 and Section Min.2 on the one-key site). Introduce Timing (section 6.2) Discuss Timing and combinational PLDs, PAL-devices and GALs Sections 6.2-6.3 11 Sep 25 Discuss Timing and combinational PLDs, PAL-devices and GALs: Sections 6.2-6.3 Homework # 8 assigned. Due on Friday. Homework 7 Due Read all previous reading assignments andSection 5.4.7 before Friday's lecture 12 Sep 27 A PAL example to help with the homework (review of Sections 6.2-6.3), then Active levels and signal names: Section 6.1.3-6.1.6, and Begin to discuss Hardware Description Languages: Section 5.1 and 5.4-5.4.1 Continue with Chapter 5-5.1 Hardware Description Languages (Skip 5.2-5.3) Section 5.4-5.4.7 -- Basics of the Verilog Hardware Description language. Some examples and details not found in the book Read Section 5.4.7 before class 13 Sep 29 Continue with Chapter 5-5.1 Hardware Description Languages (Skip 5.2-5.3) Section 5.4-5.4.7 -- Basics of the Verilog Hardware Description language. Some examples and details not found in the book Read Section 5.4.7 before class 14 Oct 2 MSI Components: Decoders (Section 6.4 in your text and Section Dec from OneKey) Homework # 9 assigned, Due Wednesday, Oct 11. A note on the reading assignments For sections 6.4-6.9, we will eventually cover all of the material on the MSI components, but skip the ABEL and VHDL sub-sections. The pattern will be to read until the topic switches to ABEL, skip the ABEL section, skip the VHDL section, then read the Verilog section. 15 Oct 4 Documentation and timing Chapter 6 - 6.1 (note that we've already covered parts of this, and 6.2) Oct 4 Optional Evening Review Session at 5:00 pm in Crothers 351. Bring questions, this is not a lecture. I do need to leave by 6:45, but we should be done before then anyway. 16 Oct 6 Exam #1 Oct 9 No Class -- Native American Day Do not forget about the Sencore Symposium on Tuesday. The bus will leave from the area north of Crothers at 8 am. We should be back before 4 pm. 17 Oct 11 Verilog Section 5.4-5.4.9 (some sections already assigned and covered) Encoders and Priority Encoders(Section 6.5 in your text and Section Enc in OneKey). Homework 9 Due Homework # 10 assigned, Due Monday 18 Oct 13 More on Encoders and Priority Encoders, briefly discuss three-state buffers. and introduce and discuss multiplexers. 19 Oct 16 Multiplexers - Section 6.7, and Exclusive-OR gates - Section 6.8 20 Oct 18 Exclusive-OR gates and Parity Circuits (Section 6.8) comparators (6.9), adders(6.10), etc In addition to covering section 6.8 and 6.9 (skipping VHDL and ABEL subsections as usual), you should: read section 6.10-6.10.2, then skim section 6.10.3-6.10.4, then read section 6.10.5, then skim section 6.10.6, and skip sections 6.10.7-6.10.9, then read section 6.10.10, then skip the remainder of Chapter 6. 21 Oct 20 Finish Comparators, begin sequential circuits (Chap 7 -7.2) Stability and meta-stability, bistable elements, S-R latches, D latches Homework # 11 assigned, and Homework # 12 assigned, both Due Monday 22 Oct 23 Introduce flip-flop (which is different from a latch!). Demo of master-slave D flip-flop. Discussed D, and J-K, and T flip-flops 23 Oct 25 Discuss T flip-flops Finite State Machines, analysis Chapter 7 through Section 7.3 Homework # 13assigned 24 Oct 27 FSM Design, Sections 7.4 and 7.5 Homework 14 Assigned for Wednesday. Homework 13 Due 25 Oct 30 FSM Design -- another example 26 Nov 1 Sequential Design with Verilog Read 7.13 through 7.13.7, skipping 7.13.4 Review Section 5.4, especially 5.4.9 Homework 14 Due Homework # 15 assigned, due on Friday. 27 Nov 3 FSM Design using Verilog (w/out a state table -- Section 7.13.5), briefly introduce your project, and discuss counters (Section 8.4 skipping VHDL parts and Section CNTR on the OneKey site). Homework 15 Due 28 Nov 6 More on MSI counters--Section CNTR on OneKey. Introduce and discuss concept of switch bounce (Sections 8.2.2-8.2.3) Nov 6 Optional evening review session in CEH 351. For now I plan to run this from 6-7. I do not mind starting earlier if the class feels that we need the time. I need to start another review session at 7:00, so this session cannot run long. I have the room reserved from 5:00 on, so we can vote on Monday (after you study over the weekend) and decide a definite start time. As usual, you should bring questions as I do not intend to lecture. 29 Nov 8 Exam II Nov 10 No Class -- Veteran's Day (Observed) 30 Nov 13 Finish with switch-bounce. Project Proposal Due by 5 pm today Last Day to Withdraw from classes 31 Nov 15 Decoding Binary Counter outputs (8.4.4) 32 Nov 17 Shift Registers, Ring Counters, Johnson Counters: Section 8.5-8.5.5, 8.5.9 Homework 16 assigned 33 Nov 20 Lab Practical logistics. Clocking and Synchronous Design Practices. 34 Nov 22 Synchronizers, synchronizer failure, better synchronizers. Homework # 17 assigned, due on Monday. Nov 24 No Class -- Day after Thanksgiving 35 Nov 27 Some outside material (everything a sophomore, non-EE digital designer needs to know about EE) Begin Chapter 9. Read 9 through Table 9-5 on the top of page 810, then skim through 9.1.4. 36 Nov 29 Basic ROM technology, EEPROM technology 37 Dec 1 RAM, SRAM, DRAM, sequential PAL-type Devices. 38 Dec 4 CPLD and FPGA internal details 39 Dec 6 Discuss Project Report/questions. Begin to analize/design a simple datapath for a simple computer. Evaluations. 40 Dec 8 Last Class Final Project Report Due If you do not have it ready by class time, you need to make an appointment to put it in my hands sometime Friday. Wednesday Dec 13 Optional Evening Review Session from 5:00 to 6:45 pm in Crothers 351. Bring questions, this is not a lecture. I do need to leave by 6:45, but we should be done before then anyway. Dec 15 Final exam -- 9 am -- Crothers 351 (Friday, December 15th)