| Week |
Lab Date |
Lab and Background Reading |
|
Aug 29 |
No Lab
|
| 1 |
Sep 5 |
Lab # 1: Introduction to TTL Data book and Logic gates
Part A (of this 3 part lab) Lab was handed out in class on Friday.
The other parts will be tutorials that you will step through, in lab, with the
TA. The only thing you need to do prior to lab is complete the truth tables in
the part handed out in class. You should also read, and adhere to,
the
Lab Report Guidelines
|
| 2 |
Sep 12 |
Lab #2: Addition and Subtraction Hardware
|
| 3 |
Sep 19 |
Lab #3: Boolean Theorems and Simplification
|
| 4 |
Sep 26 |
Lab #4: "don't care" conditions
in Karnough Maps
|
| 5 |
Oct 3 |
Lab #5: Intro to Verilog using Xilinx
It would be a very good idea to download the
Xilinx WebPack (this is free (as in gratis) software, with a registration
required. You will also need to install the patch, which is not small.
The good news is that this product should be
very compatable with they software in the lab. You can do everything at
home, except download it to the board. When you start your semester projects,
you should be able to make changes at home, clean up the compilation type
bugs, then bring it in on lab day to work out the remaining glitches.
|
| 6 |
Oct 10 |
Lab #6: Decoders
Those who are not going on
the Sencore trip will have to complete the entire lab (TTL portion and
Verilog portion) and write a report using the documentation standards
discussed in class on 10/4. Those going on the trip must complete
only the (very short) Verilog portion. Those students can do most of
the work at home, and either hand in a simulation screen shot and the Verilog
modules or demo the working program (running on the FPGA) and
hand in the code itself.
All students must hand in a soft-copy of the required Verilog modules.
|
| 7 |
Oct 17 |
Lab #7 Encoders, Priority Encoders
(and some more on Verilog and Decoders)
|
| 8 |
Oct 24 |
Lab # 8:Exclusive-Or gates, Adders, and Comparators
You won't have to have your TA show you the symbol wizard, since you've
seen this before, but some people had problems with this in that earlier lab.
Recall that "add copy of source" and "add source" are different, in that
if you "add source" any changes you make effect the original. Some people
lost work in the earlier lab this way.
Make sure both partners learn all of the steps, we have a lab practical
coming up (soon)!
|
| 9 |
Oct 31 |
Lab #9: Latches and Flip-Flops
|
| 10 |
Nov 7 |
Lab #10: Finite State Machines
|
| 11 |
Nov 14 |
Counters and Clocks
|
| 12 |
Nov 21 |
Lab Practical Exam:
Exact Schedule to be determined. Everyone will be tested today.
|