Announcements

0. I have posted a schedule for the lab practical.

1. The labs have been moved to the EE 245L -- Digital Systems Lab web page. This page is also linked below (under "Corequisites"), and that link will remain after this announcement is removed.

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@ieee.org
Phone	Office 688-4016; Home number handed out in class
Office	215 Harding Hall
Class Time	MWF 11:00-11:50
Class Location	Crothers Hall, room 351
Office hours	TBD, with your input, during the first full week of class
Text	Fundamentals of Digital Logic with Verilog Design, 2nd Edition by Stephen Brown and Zvonko Vranesic. Published by McGraw Hill The text will be supplemented with additional reference materials which will be linked from this page and/or handed out in class as they are assigned.

Corequisites

EE 245L -- Digital Systems Lab and either CsC 218 or CsC 150

Course Description

This course serves as an introduction digital logic systems. After successfully completing this course, the students will be capable of understanding, designing, and building both combinational and sequential digital systems.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will be determined using the following breakdown:

 

Exam #1	20%
Exam #2	20%
Homework and Quizzes	10%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Project(s) and Report(s)	20%
Comprehensive Final Exam	15%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.   Students are required to make a "good faith effort" on all assignments. Failure to do so will adversely effect the grade beyond the limits listed above. You must earn a grade of C or better in EE 245L this semester in order to pass this class Please read Making the Grade by Kurt Wiesenfeld and keep his views (which I share) in mind when deciding how much effort to invest in your coursework.

Schedule of Upcoming Classes

No. Date Topic, Reading, and Assignment 1 Sep 5 Introduction, go over Syllabus Skim Chapter 1, Design Concepts, and Read Chapter 2 through Section 2.3 - Variables and functions, inversion, and Truth Tables Homework # 0 assigned. 2 Sep 7 Read Sections 2.3-2.8 -- Truth Tables, Logic Gates and Networks, and Boolean Algebra, and various circuit implementations. Homework # 1 assigned, Due Wednesday September 12 Our TA situation is still in a state of flux, but we will have lab on Monday (and Tuesday). The lab is temporarily located here. A lab page will be created once the TA info is known and the lab will then be linked from that web page. Due to the TA confusion, we will be very lenient on the pre-lab requirements this week. At the very lesat, come in with a simplified circuit for the last part (Section 3.4). Do as much of the rest as you can, since it will be assigned as a "post lab" if it's not done in advance, but no points will be docked this week if the rest of the pre-lab is not completed. 3 Sep 10 Read through Section 2.7 and skim Section 2.8. Read 3.5 prior to lab. After this we will be starting Chapter 4 4 Sep 12 Karnough Maps, incompletely specified functions Read through Section 4.4 Homework # 2 assigned, Due Monday September 17 Homework #1 Due before class 5 Sep 14 Some MSI components: multiplexers Section 2.8.2 (you have already skimmed this) Transistor switches -- simple approximation Read Section 3.1, memorize Figure 3.4 Buffers and three-state buffers from the heading on page 135 to the top of page 138 Transmission gates Section 3.9 more on multiplexers Section 6.1-6.1.1, skipping example 6.2 decoders Section 6.2 skipping example 6.11 encoders Section 6.3 Homework # 3 assigned, Due Wenesday, September 19 6 Sep 17 Introduction to CAD tools/Verilog Read sections 2.9-2.10, skipping 2.10.2 Homework 2 due, prior to the start of class 7 Sep 19 Number Representation, Addition, Signed numbers, Subtraction Read Chapter 5 through Section 5.3, skipping 5.2.3 and browsing/skimming 5.3.4 only to the extent that it helps you to understand the rest of 5.3) Homework 3 due prior to the start of class. Homework # 4 assigned. Due Monday 8 Sep 21 Finish discussing overflow, Signed numbers, Subtraction (Read 5.3.4 only to the extent that it helps you understand the rest, but you will not be tested on this section. Read all of the rest of 5.3), Then start Chapter 7 on sequential circuits (latches) (read through at least Section 7.4) 9 Sep 24 Chapter 7 (through Section 7.7) Edge triggered memory elements(flip flops) Homework # 5 assigned, due Wednesday. Homework 4 due prior to the start of class. 10 Sep 26 Finite State Machines -- analysis, Chapter 8. Read through Section 8.3 and 8.9 prior to class. 11 Sep 28 Finite State Machines -- design You should read Section 8.7 in your text 12 Oct 1 More on logic optimization and minimization. Review Section 4.1, especially pages 175-176. Read 4.9 Project # 1 assigned. 13 Oct 3 Homework Discussion. Mealy vs Moore outputs. FSM debugging. Finish Quine-McClusky example. On Monday I asked you to look at some stuff in your book. By today's lecture you should be able to understand all of that material. Oct 3 Optional Review Session at 4:30 pm in CEH 351 Bring questions, this is not a lecture. 14 Oct 5 Exam #1 Oct 8 No Class -- Native American Day 15 Oct 10 More on Finite State Machines. State Minimization: Section 8.6 More on the Verilog HDL: Behavior Verilog, syntax, operators. This material is covered in Appendix A in addition to Sections 4.12 and 6.6. 16 Oct 12 More on Verilog. Section 6.6 and Appendix A 17 Oct 15 Sequential Verilog, Chapter 7 examples, shift registers and counters Homework # 6 assigned. Hand in with the results from today's lab. 18 Oct 17 Counters, ring counters, Johnson counters. Begin to discuss general FSMs in Verilog. Homework # 7 assigned for Monday. 19 Oct 19 Finish with general FSM implementation in Verilog. Begin to discuss examples in Sections 7.14.1 and 7.14.2 More information on switch bounce that you may want to consider prior to finishing your pre-lab. 20 Oct 22 Just a little more on counters and then a lot more one the examples in Section 7.14.1 and 7.14.2 Homework # 08 assigned for Wednesday. Homework 7 due 21 Oct 24 Finish with Section 7.14.1 and 7.14.2, which this weeks lab will be based on 22 Oct 26 Programmable Logic Devices (Section 3.6) BCD to seven-segment decoders (Section 6.4) Homework # 9 assigned for Monday. 23 Oct 29 Practical aspects. Noise margin, transfer characteristic, timing issues. Homework 9 due 24 Dec 25 More timing and clock issues. Homework # 10 assigned for Friday. 25 Nov 2 Synchronizer Design, issues, and failure resolution. IEEE floating point representation (Section 5.7) Homework 10 due 26 Nov 5 . . . Nov 5 Optional evening review session in CEH 351, starting at 5 pm As usual, you should bring questions as I do not intend to lecture. 27 Nov 7 Exam II Take a look at your 2nd project, which will be discussed in class on Friday. The working project is due on Monday November 19th so you will want to get started on it this weekend. 28 Nov 9 Discuss project 2 Discuss enhanced processor. Discuss Algorithmic State Machine (ASM) charts (Section 8.10) Nov 12 No Class -- Veteran's Day (Observed) 29 Nov 14 Discuss Test. Homework 11 assigned, Due on Friday 30 Nov 16 Arbiter circuit (Read 8.8, skip 8.8.1, read 8.2-8.3) Homework 11 Due Homework # 12 assigned for Monday. 31 Nov 19 Quiz on counters. More on ASM charts. Going directly from an ASM chart to an FSM using a "one hot" state assignment. Homework # 13 assigned for Wednesday. Last day to drop (with a "W") 32 Nov 21 Homework 13 due Nov 23 No class -- day after Thanksgiving 33 Nov 26 Discuss Lab and enhanced ALU. Example of using an ASM chart to design a sequential multiplier. Discussion of space/time tradeoffs. Homework # 14 assigned for Wednesday. 34 Nov 28 Some more complicated timing diagrams, discussion. 35 Nov 30 See this article which describes a project similar to what Michael spoke about today. For lab I am going to basically have you reproduce Michaels circuit which moved the square to different places on the screen, with a couple of twists. 36 Dec 3 Asynchronous sequential circuits. Read Chapter 9 through Section 9.3 and 9.6 37 Dec 5 More on asynchronous sequential circuits, glitches, hazards, and races. Homework # 15 assigned for Friday. 38 Dec 7 Comlete Chapter 9, review Chapter 10 Homework # 16 assigned for Monday. 39 Dec 10 Testing -- Chapter 11 Homework 16 Due 40 Dec 12 HW problem 9.18, design example. Teaching Evaluations. 41 Dec 14 Since our Final is first thing on Monday, we will have an in class review Dec 17 Final exam -- 9 am -- Crothers 351 (Monday, December 17th)