Announcements

1. Our server problems seem to be behind us, and the labs are now posted on a dedicated lab web page.

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@ieee.org
Phone	Office 688-4016; Home number handed out in class
Office	215 Harding Hall
Class Time	MWF 11:00-11:50
Class Location	Crothers Hall, room 351
Office hours	TBD, with your input, during the first full week of class
Text	Fundamentals of Digital Logic with Verilog Design, 2nd Edition by Stephen Brown and Zvonko Vranesic. Published by McGraw Hill The text will be supplemented with additional reference materials which will be linked from this page and/or handed out in class as they are assigned.

Corequisites

Digital Systems Lab and either CsC 218 or CsC 150

Course Description

This course serves as an introduction digital logic systems. After successfully completing this course, the students will be capable of understanding, designing, and building both combinational and sequential digital systems.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will be determined using the following breakdown:

 

Exam #1	20%
Exam #2	20%
Homework and Quizzes	10%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Project(s) and Report(s)	20%
Comprehensive Final Exam	15%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.   Students are required to make a "good faith effort" on all assignments. Failure to do so will adversely effect the grade beyond the limits listed above. You must earn a grade of C or better in EE 245L this semester in order to pass this class Please read Making the Grade by Kurt Wiesenfeld and keep his views (which I share) in mind when deciding how much effort to invest in your coursework.

Schedule of Upcoming Classes

No. Date Topic, Reading, and Assignment 1 Sep 3 Introduction, go over Syllabus Skim Chapter 1, Design Concepts, and Read Chapter 2 through Section 2.3 - Variables and functions, inversion, and Truth Tables Homework # 0 assigned. 2 Sep 5 Truth Tables, Logic Gates and Networks, and Boolean Algebra, and various circuit implementations. Read Sections 2 - 2.5, Homework # 1 assigned, Due Wednesday September 10 3 Sep 8 Some practical aspects, NMOS and PMOS transistors (as switches), NMOS and CMOS circuit s Minterms, Maxterms, more on duality. SOP and POS implementations. Read through Section 2.7 and skim Section 2.8. Compare Figure 3.48 on page 126 to Figure 2.10 in Section 2.4. Read Section 3-3.1 and enough of the surrounding text to understand Figure 3.46. Read 3.5 prior to lab. After this we will be starting Chapter 4 4 Sep 10 Discuss Lab and Homework More Algerbra and DeMorgan's Theorom. Nand-Nand and Nor-Nor implementation, Homework #1 Due before class 5 Sep 12 Karnough Maps, incompletely specified functions Read through Section 4.4 Homework # 2 assigned, Due Wednesday September 17 6 Sep 15 Some MSI components: multiplexers Section 2.8.2 (you have already skimmed this) Transistor switches -- simple approximation Read Section 3.1, memorize Figure 3.4 Buffers and three-state buffers from the heading on page 135 to the top of page 138 Transmission gates Section 3.9 more on multiplexers Section 6.1-6.1.1, skipping example 6.2 decoders Section 6.2 skipping example 6.11 encoders Section 6.3 7 Sep 17 Some more MSI components -- encoders, priority encoders Homework # 3 assigned, Due Monday, September 22 Introduction to CAD tools/Verilog Read sections 2.9-2.10, skipping 2.10.2 Homework 2 due, prior to the start of class 8 Sep 19 More on Verilog (see Wednesday's readding assignment) Start with Number Representation, Addition, Read Chapter 5 through Section 5.3, skipping 5.2.3 and browsing/skimming 5.3.4 only to the extent that it helps you to understand the rest of 5.3) 9 Sep 22 Number conversions, including fractions. Signed numbers, Subtraction Homework # 4 assigned. Due Friday 10 Sep 24 Finish discussing overflow, Signed numbers, Subtraction (technique and hardware) (Read 5.3.4 only to the extent that it helps you understand the rest, but you will not be tested on this section. Read all of the rest of 5.3), Outline of need for sequential circuits 11 Sep 26 Chapter 7 (through Section 7.7). Sequential Circuits. Latches. Edge triggered memory elements(flip flops) Homework # 5 assigned, due Wednesday. Homework 4 due prior to the start of class. 12 Sep 29 Finish with Edge triggered memory elements(flip flops), completing through Section 7.7 We will come back to Chapter 7 later, but we will first touch on Finite State Machines (in Chapter 8) Finite state machines, analsysis 13 Oct 1 Finite State Machines -- design, Chapter 8. Read through Section 8.3 and 8.9 prior to class. Homework 5 due prior to the start of class. Homework 6 due prior to the start of class. Homework # 7 assigned, due Monday. Oct 1 Optional evening review session in probably CEH 351, probably starting around 6:30 pm You should bring questions as I do not intend to lecture. 14 Oct 3 Exam #1 15 Oct 6 More on the Verilog HDL: Behavior Verilog, syntax, operators. This material is covered in Appendix A in addition to Section 6.6 of your textbook. I will wait to assign your project after labs this week. Homework 7 Due 16 Oct 8 Lab discussion, FSM Debugging More on the Verilog HDL: procedural Verilog, syntax, operators. This material is covered in Appendix A in addition to Sections 4.12 and 6.6. 17 Oct 10 Brief discussin of 5- and 6- variable Karnaugh Maps (Section 4.1). Discuss project # 1 Then discuss Sequential Verilog, Chapter 7 examples, shift registers and counters Oct 13 No Class -- Native American Day 18 Oct 15 Counters, ring counters, Johnson counters. Begin to discuss general FSMs in Verilog. 19 Oct 17 Self correcting ring counters and Johnson counters. Homework # 9 assigned for Wednesday. 20 Oct 20 General FSM implementation in Verilog. 21 Oct 22 Read Sections 3.5-3.7 and Section 6.4 Discuss Programmable Logic Devices (Section 3.6) and BCD to seven-segment decoders (Section 6.4) Homework # 10 assigned for Monday. 22 Oct 24 Finish w/ programmable logic, and begin to discuss timing issues. 23 Oct 27 Timing issues in both combitational and sequential logic Homework # 11 assigned for Friday. 24 Oct 29 Quine McCluskey (tabular) method for Minimization Read Section 4.8 (for background and terminology) and read 4.9 in detail for the actual method. Realize that this is much more likely to be implemented via a computer program than "by hand". Homework # 12 assigned for Monday. 25 Dec 25 Simple Data Path and processor -- Sections 7.14.1 and 7.14.2 26 Nov 3 project report due -- extended until class time today Homework 12 due . . . . . . . . . Nov 5 Optional Evening Review Session at 5:30 pm in CEH 351. Please bring questions, this is not a lecture 28 Nov 7 Exam II Project # 2 assigned 29 Nov 10 State Minimization - Section 8.6-8.6.1 We will not cover 8.6.2 at this time. Static and dynamic hazards - Section 9.6-9.6.3 30 Nov 12 Design example using state diagrams and transition lists/transiton equations. Homework 13 (in class handout) assigned for Friday. Nov 14 Brief administrative meeting on Lab Practical and schedule. Homework 13 due Class basically cancelled. 31 Nov 17 Clock and timing issues. Synchronizing inputs to your clock. Predicting synchronizor failure rates. Last day to drop with a "W" (withdraw) 32 Nov 19 more on synchronizor failure and designing better syncrhonizor. 33 Nov 21 Dealing with switch bounce, several additional approaches. Discuss VGA lab. 34 Nov 24 Asynchronous sequential machines -- Chapter 9 (read through 9.4) 35 Nov 26 More on asynchronous sequential machine analysis, begin design of asynchronous machines. Chapter 9 through 9.4 Nov 28 No Class. Day after Thanksgiving. 36 Dec 1 Design of asynchronous sequential machines. Homework # 14 assigned for Friday. 37 Dec 3 Design of asynchronous sequential machines, textbook examples. 38 Dec 5 Design of asynchronous sequential machines. Hand in 9.17 39 Dec 8 Testing -- Chapter 11 Hand in 9.18 . . . . . . . . . Dec 15 Optional Review Session. 11:00 am, in CEH 351 Dec 16 Final exam -- 9 am -- Crothers 351 (Tuesday, December 16th)