Announcements

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@ieee.org
Phone	Office 688-4016; Home number handed out in class
Office	215 Harding Hall
Class Time	MWF 2:00-2:50
Lab Time	The lab will be reserved for this class on Fridays from 3:00-6:50
Class Location	Harding Hall, room 326
Office hours	TBD
Textbook	Computer Organization, fifth edition by Carl Hamacher, Zvonko Vranesic, and Safwat Zaky, published by McGraw Hill. For brevity, I will refer to this as HVZ
Reference	Some subset of the following books would prove a valuable reference. Do not buy any of these before speaking w/ Dr. Fourney. Digital Design: Principles & Practices 4th Ed. by John F. Wakerly, published by Prentice Hall (W4e) You will want to refer back to this book if you used if for Digital Design. If you used an earlier edition you should note that the fourth edition also serves as a Verilog reference. The earlier editions are actually better and more complete as digital references, since Prentice Hall put some material on a (poorly thought out, poorly implemented, insecure, subscription based) website in order to make room for the Verilog. So, if you already have access to this book that's a good thing, but if you need to go buy a reference this is not the one to buy. Since most of you do already own this book, I will reference relevant sections and refer to is as W4e. If you own an earlier edition, the stuff I refer to will probably be in your book somewhere, see me if you have trouble finding it. If you don't have access to W4e, you can probably find sufficient Verilog info on the web, but if you feel you need to buy another textbook you could look into: Starters Guide to Verilog 2001, by Michael D. Ciletti (also by Prentice Hall). This is a good Verilog reference, which assumes you already understand digital design. or Digital Logic with Verilog Design, by Stephen Brown and Zvonko Vranesic. This is an excellent textbook which we have adopted for our 245 class. It combines digital design and Verilog in the same text, and you actually buy all of the content instead of renting it via a web site. Verilog 2001: A Guide to the New Features of the Verilog Hardware Description Language by Stuart Sutherland. I have not actually seen this book, but the author is well respected in this area and has provided several free online tutorials on the Verilog Hardware Description Language.

Corequisites

The "hands on" portion of this class, EE 492 Section 03, is a required co-requisite. You must be enrolled in both classes.

Course Description

This course serves as an introduction to computer organization. We basically fill in the gaps between your digital systems class (EE 245) and your microcontroller class (EE 347). We show you how to take what you learned in 245 and design the systems you used in 347. We'll discuss various design trade-offs, optimizations, and enhancements to computer designs. After successfully completing this course, the students will be capable of understanding, designing, and building simple computers and will be cognizant of the current trends and design techniques in this area.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will probably be determined via the following breakdown:

 

Exam #1	15%
Exam #2	15%
Homework and Quizzes	15%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Projects & reports	25%
Comprehensive Final Exam	15%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.

Schedule of Upcoming Classes

No. Date Topic, Reading, and Assignment 1 Sep 3 Introduction to Computer Organization (what to expect), go over Syllabus and grading scheme, discuss logistics, schedule lab Read Chapter 1 in HVZ 2 Sep 5 Computer Organization. Chapter 1 of HVZ Lab 01 Sep 5 This is time for you to get (re)aquainted with our DE2 boards and review Verilog. Here are some handy Verilog references: this one is by Stuart Sutherland and highlights the useful differences between the old and new Verilog. here is a Verilog reference from the same source. The same author has also published books in this area. If your EE 245 book is not a suitable Verilog reference you may consider purchasing Verilog 2001: A Guide to the New Features of the Verilog Hardware Description Language If anybody learned Verilog "back in the day" they might also want to consult his Verilog-1995 Quick Reference Guide (I often use this, since it's a closer match to the language I learned) 3 Sep 8 Introduction or Rapid Review of Verilog. Read Sections 5-5.1 and 5.4 of W4e, or Verilog Tutorial, or equivalent. Note that this tutorial doesn't follow the active level signal naming convention that we've used in the past. Let's get in the habit of appending an "_L" to signal names which are active low. The Verilog compiler doesn't care, but it makes it much easier for somebody else to follow your code. For example, using this convention we would name an active low reset signal reset_L 4 Sep 10 Verilog for sequential circuits and finite state machines, continued introduction to Computer Organization (discuss Chapter 1 in HVZ) . . . . . . . . . Lab 02 Sep 12 For lab today we will start to work our way through Lab 9 and Lab 10 from a 245-ish course based on the Altera boards. I have not verified (read "attempted") to do Part II w/ the new version of the Altera Software. You may work together and share results/discoveries on Part II only. Do not share code on any of the other parts, but feel free to share ideas and concepts. Do not panic if you do not completely finish the lab. You should all get through Part III, and should all attempt to get as much done as possible. Try to write good HDL code, we will expand to a 16-bit instruction word and an ALU with more functionality (See Figure 7.1 in HVZ) for later labs. If you keep this in mind this week you will be able to re-use much of your HDL code. . . . . . . . . . Lab 03 Sep 19 Finish Lab 02 after demonstrating your EE 245 pop machine (or equivalent if you didn't take EE 245 here). 9 Sep 22 Basic I/O, subroutine calls, encoding machine instructions Done w/ Chapter 2 except for linked lists 10 Sep 24 Finish w/ Chapter 2 (linked lists) Skip Chapter 3, for now Chapter 4-4.2 I/O and interrupts . . . . . . . . . Lab 04 Sep 26 Continue working on and improving your datapath/processor 12 Sep 29 Interupt arbitration, DMA implementation 13 Oct 1 Distributed Arbitration (clarifying example). I/O timing details, Input Port design (hardware). 14 Oct 3 Output Port, Hardware Design. General purpose (bidirectional) port design, serial port hardware. Lab 05 Oct 3 15 Oct 6 Algorithmic State Machine (ASM) diagrams. 16 Oct 8 Memory technology, memory management, cache (5 - 5.5) 17 Oct 10 More on cache (Section 5.5-5.6) HVZ 5.13 and 5.14 assigned for Wednesday Oct 13 No Class -- Native American Day 18 Oct 15 More on cache, virtual memory, memory management unit (MMU) (Chapter 5) . . . . . . . . . May 8 Final exam -- 9 am -- Harding 326 (Friday, December 19th)