Announcements

1.By popular request, the due-date for your Project 1 report has been extended till class time on Monday, November 9th.

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@ieee.org
Phone	Office 688-4016; Home number handed out in class
Office	ECS 221
Class Time	MWF 9:00-9:50
Class Location	Crothers Hall, room 351
Office hours	TBD, with your input, during the first full week of class
Text	Fundamentals of Digital Logic with Verilog Design, 2nd Edition by Stephen Brown and Zvonko Vranesic. Published by McGraw Hill The text will be supplemented with additional reference materials which will be linked from this page and/or handed out in class as they are assigned.

Corequisites

EE 245L -- Digital Systems Lab and either CsC 218 or CsC 150

Course Description

This course serves as an introduction digital logic systems. After successfully completing this course, the students will be capable of understanding, designing, and building both combinational and sequential digital systems.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will be determined using the following breakdown:

 

Exam #1	20%
Exam #2	20%
Homework and Quizzes	10%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Project(s) and Report(s)	20%
Comprehensive Final Exam	15%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.   Students are required to make a "good faith effort" on all assignments. Failure to do so will adversely effect the grade beyond the limits listed above. You must earn a grade of C or better in EE 245L this semester in order to pass this class Please read Making the Grade by Kurt Wiesenfeld and keep his views (which I share) in mind when deciding how much effort to invest in your coursework.

Schedule of Upcoming Classes

No. Date Topic, Reading, and Assignment 1 Sep 2 Introduction, go over Syllabus Skim Chapter 1, Design Concepts, and Read Chapter 2 through Section 2.3 - Variables and functions, inversion, and Truth Tables Homework # 0 assigned. 2 Sep 4 Truth Tables, Logic Gates and Networks, and Boolean Algebra, and various circuit implementations. Read Sections 2 - 2.5, Read 3.5 prior to lab. Sep 7 No Class -- Labor Day 3 Sep 9 Boolean Algebra, and various circuit implementations. Read Sections 2 - 2.5, Homework # 1 assigned, Due Friday September 11 4 Sep 11 Discuss more results from lab. Some practical aspects, NMOS and PMOS transistors (as switches), NMOS and CMOS circuit s Minterms, Maxterms, more on duality. SOP and POS implementations. Read through Section 2.7 and skim Section 2.8. Compare Figure 3.48 on page 126 to Figure 2.10 in Section 2.4. Read Section 3-3.1 and enough of the surrounding text to understand Figure 3.46. Homework #1 Due before class After this we will be starting Chapter 4 5 Sep 14 Karnough Maps, incompletely specified functions Read through Section 4.4 Homework # 2 assigned, Due Friday September 18 6 Sep 16 Some MSI components: multiplexers Section 2.8.2 Transistor switches -- simple approximation Read Section 3.1, memorize Figure 3.4 Buffers and three-state buffers from the heading on page 135 to the top of page 138 Transmission gates Section 3.9 more on multiplexers Section 6.1-6.1.1, skipping example 6.2 decoders Section 6.2 skipping example 6.11 encoders Section 6.3 7 Sep 18 Some more MSI components -- encoders, priority encoders Homework # 3 assigned, Due Wednesday, September 23 Homework 2 due, prior to the start of class 9 Sep 23 More on Verilog (see Monday's reading assignment) Start with Number Representation, Addition, Read Chapter 5 through Section 5.3, skipping 5.2.3 and browsing/skimming 5.3.4 only to the extent that it helps you to understand the rest of 5.3) Homework # 3 Due before class 10 Sep 25 Start with Number Representation, Addition, Read Chapter 5 through Section 5.3, skipping 5.2.3 and browsing/skimming 5.3.4 only to the extent that it helps you to understand the rest of 5.3) Number conversions, including fractions. Signed numbers, Subtraction Homework # 4 assigned. Due Wednesday. We've really only covered enough for you to do 5.1-5.4 at this point, and will cover the rest on Monday. Note that you do not need to hand in 5.1-5.5, but are strongly encouraged to look at them 11 Sep 28 Finish discussing overflow, Signed numbers, Subtraction (technique and hardware) (Read 5.3.4 only to the extent that it helps you understand the rest, but you will not be tested on this section. Read all of the rest of 5.3), 12 Sep 30 Chapter 7 (through Section 7.7). Sequential Circuits. Latches. Homework # 5 assigned due Monday. Homework 4 due prior to the start of class. 13 Oct 2 Edge triggered memory elements(flip flops), completing through Section 7.7 Our Test on Wednesday will cover through today, including the homework that is due on Monday. Note that I did not assign homework 6 yet, and it will not be included on the test. We are done with Chapter 7 for now. We will come back to Chapter 7 later, but we will first touch on Finite State Machines (in Chapter 8) 14 Oct 5 Finite state machines, and analsysis of same Homework 5 due prior to the start of class. Homework # 6 assigned, due Friday. Oct 5 Optional Evening Review Session at 5:30 pm in SECS 0218 Please bring questions, this is not a lecture Note that this is not our regular classroom 15 Oct 7 Exam #1 16 Oct 9 Finite State Machines. Design Methodology and Example. Before class you should read 8-8.3 and Section 8.9 Homework 6 Due before class Homework # 7 assigned, due Tuesday. Project # 1 assigned. Note that there are some very short-term deliverables. Oct 12 No Class -- Native American Day 17 Oct 14 Lab discussion, FSM Debugging Brief discussin of 5- and 6- variable Karnaugh Maps (Section 4.1). Quine McCluskey (tabular) method for Minimization Read Section 4.8 (for background and terminology) and read 4.9 in detail for the actual method. Realize that this is much more likely to be implemented via a computer program than "by hand". 18 Oct 16 Read Sections 3.5-3.7 and Section 6.4 Discuss Programmable Logic Devices (Section 3.6) and BCD to seven-segment decoders (Section 6.4) Homework # 8 assigned for Wednesday. 19 Oct 19 Finish w/ programmable logic, and a discussion of memory 20 Oct 21 Timing Issues. Homework 8 Due Homework # 9 assigned for Wednesday. 21 Oct 23 More on the Verilog HDL: Behavioral Verilog, syntax, operators. This material is covered in Appendix A in addition to Sections 4.12 and 6.6 of your textbook. 22 Oct 26 Continue with Behavioral Verilog/Procedural Verilog, syntax, operators, etc. This material is covered in Appendix A in addition to Sections 4.12 and 6.6 of your textbook. 23 Oct 28 Begin discussion on using procedural Verilog for sequential components and circuits (Chapter 7) 24 Oct 30 Sequential Verilog, Chapter 7 examples, shift registers and counters. Begin to discuss general FSMs in Verilog. Here is a soft copy of a practice exam 25 Nov 2 Discussed switch bounce and possible solutions. More information on switch bounce that you may wish to consider before coming to lab tomorrow. 26 Nov 4 Decoding counter outputs, glitch-free solution, ring counters Self-correcting ring-counters, Johnson Counters, self-correcting Johnson-counters Nov 4 Optional Evening Review Session at 7:00 pm in SECS 0218 Note time and location has changed! Please bring questions, this is not a lecture 27 Nov 6 Exam II 28 Nov 9 Project Reports Due in Class (deadline extended until class time today) Read: Section 7.14.1-7.14.2 (Design Example), Section 8.2, Section 8.8, and Section 8.10 Homework # 11 posted, now due Friday. Homework # 12 assigned, also due Friday. Nov 11 No Class -- Veteran's Day 29 Nov 13 Hand Back Exam Homework 11 and Homework 12 due 30 Nov 16 Discuss upcoming labs More on the simple processor -- derive control signals Sections 7.14.1 and 7.14.2 Last day to drop with a "W" (withdraw) 31 Nov 18 Clock and timing issues. Synchronizing inputs to your clock. Predicting synchronizor failure rates. 32 Nov 20 more on synchronizor failure and designing better syncrhonizor. Project # 2 formally assigned. . . . . . . . . . Dec 14 Final exam -- 9 am -- Crothers 351 (Monday, December 14th)