Homework 12   Also Due on Friday, November 13th.


Thes problems refer to the arbiter FSM shown in Figure 8.72 
(and/or 8.73) in your text. You are to design this circuit using:

1. A state assignment which minimizes the number of flip-flops, and
2. a "one hot" state assignment.

3. Assume that both of your circuits (from 2 and 3 above)  are to be 
implemented from discrete components, using the 74LSXX family (74LS74 
flip-flops, 74LSXX and-gates, or-gates, whatever).  Calculate the 
delays from the rising clock edge until the "grant" signals are asserted 
for each circuit.  

You might want to refer to Figures 8.76 and 8.77 in your book.