Announcements

1. We have an optional review session in Crother's 358 at 1:00 pm on Tuesday, May 3rd. Bring questions, this is not a lecture.

2. Our Final Exam is on Thursday, May 5th at 9 am in Solberg 102.

3. Daktronics is looking for student workers. Although the posting doesn't make it obvious, they are looking for a sophomore level EE student, and they will train you for the job. The person who held this particular job for the last 3 years recommends it highly. In fact, he's the one who sent me the announcement.

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@sdstate.edu
Phone	688-4016
Office	215 Harding Hall
Class Time	MWF 8:00-9:50
Class Location	Solberg Hall, room 102
Office hours	To be determined the first full week of class Please do not disturb MWF 7-8 or 11-12 Other times by available by appointment
Text	Digital Design: Principles & Practices 3rd Ed. by John F. Wakerly, published by Prentice Hall Companion Web Site: ddpp.com The text will be supplemented with additional reference materials which will be linked from this page and/or handed out in class as they are assigned.

Corequisites

EE 245L -- Digital Systems Lab

Course Description

This course serves as an introduction digital logic systems. After successfully completing this course, the students will be capable of understanding, designing, and building digital systems.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will be determined via the following breakdown:

 

Exam #1	20%
Exam #2	20%
Homework and Quizzes	10%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Project and PDR	15%
Comprehensive Final Exam	20%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.   Please read Making the Grade by Kurt Wiesenfeld and keep his views (which I share) in mind when deciding how much effort to invest in your coursework.

Schedule of Upcoming Classes

No. Date Topic, Reading, and Assignment 1 Jan 12 Introduction, go over Syllabus Skim Chapter 1 Homework # 1 assigned. 2 Jan 14 Introduce Positional Number systems and discuss first lab Chapter 2 - 2.4 Homework #2 will be assigned on Wednesday Jan 17 No Class -- Martin Luther King, Jr. Day Holiday 3 Jan 19 Addition and subtraction --Section 2.4 Representation of negative numbers Section 2.5 except2.5.7 Homework # 2 assigned. 4 Jan 21 Addition and subtraction w/ negative numbers - section 2.6 and (with much less emphasis) 2.7 Binary Coded Decimal (first 5 paragraphs of Section 2.10 only) Gray Code --Section 2.11 We will eventually cover chapter 2 through section 2.13 (ending at the bottom of page 56), skipping sections 2.5.7, 2.8, and 2.9. Homework 2 due, Homework # 3 assigned. Due Monday 5 Jan 24 Finish Chapter 2 Briefly discuss ASCII - Section 2.12 Briefly discuss parity- Last paragraph on page 59 to Section 2.15.2 (including Table 2-13) Chapter 3. Digital abstraction. Logic circuit as black box. Truth Tables, logic gates, fan-out, delays (You should read sections 3-3.1, 3.4-3.4.1, 3.5.6, 3.5.8, blue box on pg 113, Figure 3.36 on page 114--This is ALL that we will cover in Chapter 3 for now) Homework 3 due before class, in the front of the room For next time, look at problems 2.23 and 3.5. You do not need to hand these in, but if you don't understand them you should ask before class on Wednesday. Also start reading Chapter 4. 6 Jan 26 Chapter 4. Boolean Algebra. Axioms and Theorems. Homework # 4 assigned. Due on Friday 7 Jan 28 Duality, DeMorgan's theorem, literals, terms, minterms, and maxterms Skip the example from midway down page 204 through the beginning of section 4.1.6, but read all the rest of chapter 4 through section 4.2 before class on Monday Homework # 5 (Problem 4.6) assigned. Due Monday 8 Jan 31 Continue with terminology: literal, product term, sum term, minterm, maxterm, canonical sum, canonical product, minterm list, maxterm list, etc. Sum of products and product of sums implementation. Homework # 6 assigned. Due Wednesday 9 Feb 2 Sum of products and product of sums implementation. More algebra. Introduce Nand-Nand and Nor-Nor constructions. Covered Through section 4.2 10 Feb 4 Karnough Maps, prime implicant theorem, SOP and POS solutions Sample exam (from last semester) handed out and briefly discussed Sections 4.3 - 4.3.7 11 Feb 7 Finish up POS, introduce "don't care" conditions. (Sections 4.3.6-4.3.7) Begin Chapter 5 - Documentation Problem 4.19 a,b, c assigned, due Wednesday (later postponed) 12 Feb 9 What to expect on test, Introduce Chapter 5 - Documentation Today's assignment postponed, hand it in with Homework # 7, which is due Monday 2/14 Feb 9 Optional Evening Review Session. 5:00 pm in Solberg 102 13 Feb 11 Exam #1 14 Feb 14 Chapter 5 - Documentation Handed Test back (happy Valentine's Day) Homework 7 Due Homework # 8 assigned, Due Wednesday 15 Feb 16 Circuit timing (Should now have read Chapter 5 through Section 5.2) PLDs, PAL-devices and GALs Chapter 5.3-5.3.3, skip 5.3.4, 5.3.5. SKIM 5.3.6 Homework # 9 assigned, Due Friday 16 Feb 18 MSI Components: Decoders and Encoders Homework Due Homework # 10 assigned, Due Wednesday Feb 23 Feb 21 No Class. President's Day Holiday 17 Feb 23 Priority Encoders and three-state devices Homework # 11 (Problem 5.20) assigned, Due Friday Feb 25 Homework Due 18 Feb 25 More on three-state devices. Introduce multiplexers and exclusive-or gates. Sections 5.6-5.6.2 and 5.7-5.7.3 Homework # 12 (Problems 5.21 and 5.22) assigned, Due Monday Feb 28 19 Feb 28 More on ex-or gates: parity circuits, comparators, adders, etc Sections 5.8 through the second paragraph on page 415, 5.9-5.9.4, 5.10-5.10.2, skim 5.10.3-5.10.4. Skip Section 5.11 Homework # 13 (Problems 5.12, 5.27, and 5.28) assigned, Due Wednesday Mar 2 20 Mar 2 Combinational design example Sections 6-6.1.1 -- Barrel Shifter Example and 6.1.3 Dual priority encoder (skipped rest of Chapter 6) No written homework 21 Mar 4 Sequential Circuits. Stability and meta-stability, bistable elements, S-R latches Homework # 14 (Problems 7.2 and 7.3) assigned, Due Monday, Mar 14 Mar 7 No Class, Spring Break Mar 9 No Class, Spring Break Mar 11 No Class, Spring Break 22 Mar 14 D latches, Introduce flip-flop (which is different from a latch!) Discussed D and J-K flip-flops. Homework 15 handed out in class, due on Wednesday Exam will cover through section 7.2.6, excluding Figure 7-20 23 Mar 16 Finish with J-K flip-flops (Section 7.2.10) and discuss T Flip-Flops (Section 7.2.11, note that we skipped sections 7.2.7-7.2.9) Begin State Machines (Section 7.3) Homework 15 due before class Mar 16 Optional review session at 5:00 PM in Solberg 128 24 Mar 18 Exam 25 Mar 21 Finite State Machine Analysis Chapter 7: Sections 7 -7.3 and perhaps design (Section 7.4) Homework # 16 assigned, Due Wednesday, Mar 23 26 Mar 23 Finite State Machine Design: Sections 7.4-7.5 Your project, which may be assigned today, will be based on this topic Mar 25 No Class -- Easter Recess Mar 28 No Class -- Easter Recess 27 Mar 30 More design- unused states, design process, ambigious specifications, other design decisions Project Discussion 28 Apr 1 More FSM design examples 29 Apr 4 More FSM design examples, Mealy vs Moore output nuances, string detector 30 Apr 6 SSI latches and flip-flops, Switch bounce and potential cures Sections 8.2-8.2.3 31 Apr 8 Multibit Registers and Latches, Counters Section 8.2.5, and 8.4-8.4.4 32 Apr 11 Finish up counters (8.4.3-8.4.4), discuss various clock issues (Section 8.8-8.8.2) 33 Apr 13 Finish with clock issues (gating of clock signals), discuss shift registers (Section 8.5-8.5.3) 34 Apr 15 shift registers, ring counters and Johnson counters (Section 8.5-8.5.7, skipping 8.5.4) 35 Apr 18 Decomposition of state machines 36 Apr 20 Syncronization of Asynchrnous inputs and synchronizer failure 37 Apr 22 More on synchronizer failure, design of better syncrhonizers. student surveys 38 Apr 25 Finish with better syncrhronizer design 39 Apr 27 Static one hazards - Section 4.5-4.5.2 Memory, types of memory Sections 10-10.1.4, 10.2-10.3.2, 10.4-10.4.1 Then re-read 10.1.4 (hint) 40 Apr 29 Complex PLDs: Sections 10.5-10.5.2, with particular attention to Figures 10-37 and 10-40 and Table 10-8. Re-read the blue box (bottom of page 881) on "Pin Locking". FPGAs: Sections 10.6 with particular attention to Figures 10-43 and 10-44. May 3 Optional Review Session in Crother's 358 at 1:00 pm Bring questions, this is not a lecture. May 5 Final exam -- 9 am -- Solberg 102 (Thursday, May 5)