Announcements

1. Please mail the prelab to ee245Lsdsu@gmail NOT the address I put in the lab.

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@sdstate.edu
Phone	Office 688-4016; Home number handed out in class
Office	215 Harding Hall
Class Time	MWF 11:00-11:50
Class Location	Crothers Hall, room 351
Office hours	To be determined the first full week of class
Text	Digital Design: Principles & Practices 4th Ed. by John F. Wakerly, published by Prentice Hall There is a subscription based companion web site (so don't throw away the stuff that is packaged with your new book!). We will discuss how to access this site in class. A better, web resource can be found at: ddpp.com. This is the author's web site for an earlier version of the book. It is a much better web site, but (obviously) refers to a different (but similar) book. For example, you might find a problem solution to a problem in your book but the problem number will be different. You'll probably need to make use of both, since Prentice Hall saved some printing expense by putting some ``optional'' material on the web but not in the book. The text will be supplemented with additional reference materials which will be linked from this page and/or handed out in class as they are assigned.

Corequisites

EE 245L -- Digital Systems Lab

Course Description

This course serves as an introduction digital logic systems. After successfully completing this course, the students will be capable of understanding, designing, and building both combinational and sequential digital systems.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will probably be determined via the following breakdown:

 

Exam #1	20%
Exam #2	20%
Homework and Quizzes	10%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Project and PDR	15%
Comprehensive Final Exam	20%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.   Please read Making the Grade by Kurt Wiesenfeld and keep his views (which I share) in mind when deciding how much effort to invest in your coursework.

Schedule of Upcoming Classes

No. Date Topic, Reading, and Assignment 1 Jan 18 Introduction, go over Syllabus Skim Chapter 1 Homework # 1 assigned. 2 Jan 20 Introduce Positional Number systems and discuss first lab Chapter 2 - 2.4 Homework 2 assigned, due on Wednesday, January 25th Part A (of a 3 part lab) Lab was handed out in class. The other parts will be tutorials that you will step through, in lab, with the TA. The only thing you need to do prior to lab is complete the truth tables in the part handed out in class today. 3 Jan 23 Addition and subtraction --Section 2.4 Representation of negative numbers Section 2.5 except2.5.7 Homework # 3 assigned. 4 Jan 25 Addition and subtraction w/ negative numbers - section 2.6 and (with much less emphasis) 2.7 Binary Coded Decimal (first 5 paragraphs of Section 2.10 only) Gray Code --Section 2.11 We will eventually cover chapter 2 through section 2.13 (ending at the bottom of page 56), skipping sections 2.5.7, 2.8, and 2.9. Homework # 4 assigned, due Monday. Homework 2 due, prior to the start of class 5 Jan 27 Finish Chapter 2 Briefly discuss ASCII - Section 2.12 Briefly discuss parity- Last paragraph on page 59 to Section 2.15.2 (including Table 2-13) Chapter 3. Digital abstraction. Logic circuit as black box. Truth Tables, logic gates, fan-out, delays (You should read sections 3-3.3.1, definition of "fan in" on page 92 (section 3.3.5), fan out (3.5.4), all of 3.5.7 (including the box on page 114) Discussion of Figure 3-36 on page 115, Fig 3-39 (118) and 3-41 (119). (This is ALL that we will cover in Chapter 3 for now) Homework 3 due prior to the start of class. 6 Jan 30 Chapter 4-4.1.3. Boolean Algebra, Axioms and Theorems. Homework # 5 assigned. Due on Friday Homework 4 Due 7 Feb 1 Duality, DeMorgan's theorem, literals, terms, minterms, maxterms, canonical sum, canonical product, minterm list, maxterm list, etc. Homework # 6 assigned. Due on Monday 8 Feb 3 Went over homeworks on signed number systems and algebra. Went over next Tuesday's lab. Did design based on a verbal description. 9 Feb 6 More algebra. Introduce Karnough Maps (Section 4.3.4) 10 Feb 8 Prime implicant theorem, SOP and POS solutions, introduce "don't care" conditions. (Sections 4.3.4-4.3.6 in your text, plus sections Min.1 and Min.2 on the one-key site). Homework # 7 assigned. Due on Friday Note: Consult your class notes from 2/1 before attempting to access OneKey. After that, go to the OneKeysite to register and/or login. Remember that all of the web designers at Prentice Hall failed "computer security 101" and any password you select will be stored in the clear on their machines and emailed back to you in cleartext. DO NOT "reuse" a password from another system. Once you gain access, you should start in the "Course Documents" section (this should happen automatically after you login) About 2/3 of the way down this page there is a hyperlink labeled "Min: Other Minimization Topics". Click that, then click the link for "Supplementary Section (PDF)". Then read sections Min.1 and Min.2. Their web server seems balky, in that I had to hit "reload" two or three times to get a valid PDF file. 11 Feb 10 Karnough Maps Continued. More on SOP and POS solutions, introduce "don't care" conditions. (Sections Min.1 and Min.2 on the one-key site). Circuit Timing -- Section 6.2 Homework 7 due Homework # 8 assigned. Due on Monday 12 Feb 12 Review homework problems, work K-map problems on board. Discuss minimal SOP, vs POS, and use of don't cares. Homework 8 due 13 Feb 15 Timing and combinational PLDs, PAL-devices and GALs Sections 6.2-6.3 Homework # 9 assigned. Due on Wednesday, Feb 22 Reading assignment: Before lab on Tuesday read 5-5.1, 5.4-5.4.1, 5.4.7-page 308, and 6.1.3. This is in addition to whatever you might need to read to do your your homework. Feb 15 Optional Evening Review Session at 5:00 pm in Crothers 351. Bring questions, this is not a lecture. 14 Feb 17 Exam #1 Feb 20 No Class -- President's Day Holiday 15 Feb 22 More on combinational PLDs, PAL-devices and GALs (Section 6.3) MSI Components: Decoders (Section 6.4 in your text and Section Dec from OneKey) Homework # 10 assigned, Due Monday (but there will probably be more problems assigned for Monday) A note on the reading assignments For sections 6.4-6.9, we will cover all of the material on the MSI components, but skip the ABEL and VHDL sub-sections. The pattern will be to read until the topic switches to ABEL, skip the ABEL section, skip the VHDL section, then read the Verilog section. Homework 9 Due 16 Feb 24 Documentation Section 6.1 No additional homework assigned, Homework # 10 is still due Monday 17 Feb 27 Finish up with Documentation, begin to discuss Hardware Description Languages (HDLs). A "do over" on the PAL part of Homework # 9 assigned. Due Friday Make sure that you've read up on Verilog (by now you should have read Chapter 5 through Section 5.2, 5.3-5.3.3, skipped 5.3.4, 5.3.5, and SKIMMED 5.3.6) Homework Due 18 Mar 1 Verilog (Chapter 5 through Section 5.2, 5.3-5.3.3, skipped 5.3.4, 5.3.5, and SKIMMED 5.3.6) 19 Mar 3 Some more Verilog examples, then Encoders and Priority Encoders(Section 6.5 in your text and Section Enc in OneKey). Also read Section 6.6 on three-state devices which we've already been exposed to. Introduce and discuss multiplexers. Homework # 12 assigned, Due Monday, March 13th Homework 11 (Do-over of PAL part of Homework 9) due Mar 6 No Class. Spring Break Mar 8 No Class. Spring Break Mar 10 No Class. Spring Break 20 Mar 13 Review Priority Encoders 21 Mar 15 More on three-state devices. Discuss Verilog conditional assignment operator and the implementation of three-states, transceivers, muxes. 22 Mar 17 Exclusive-or gates: parity circuits, comparators, adders, etc In addition to covering section 6.8 and 6.9 (skipping VHDL and ABEL subsections as usual), you should: read section 6.10-6.10.2, then skim section 6.10.3-6.10.4, then read section 6.10.5, then skim section 6.10.6, and skip sections 6.10.7-6.10.9, then read section 6.10.10, then skip the remainder of Chapter 6. 23 Mar 20 Begin Chapter 7 Sequential Circuits. Stability and meta-stability, bistable elements, S-R latches, D latches Homework # 13 assigned, Due Wednesday Mar 22 by 5pm, and Homework # 14 assigned, Due Wednesday Mar 22 prior to class. 24 Mar 22 Introduce flip-flop (which is different from a latch!). Demo of master-slave D flip-flop. Discussed D, J-K, and T flip-flops 25 Mar 24 Discuss previous homework. Hand out and discuss practice exam as well as what would be on upcoming test. 26 Mar 27 Finite State Machines, analysis Chapter 7 through Section 7.3 Mar 27 Optional Review session at 6:00 PM in CEH 307 27 Mar 29 Exam # 2 Mar 31 Class cancelled so that you all can attend the Engineering Expo in Frost Arena 28 Apr 3 FSM Design, Sections 7.4 and 7.5 Homework Due -- 2 sets 29 Apr 5 More FSM Design, using Verilog for implementation once a machine is designed Homework # 17 assigned. Due on Friday 30 Apr 7 FSM Design using Verilog (w/out a state table), discuss project. Homework 17 Due 31 Apr 10 Address Project questions, discuss counters, discuss lab practical, and discuss 7-segment display (on digi-IO boards) and time multiplexing. 32 Apr 12 Discuss switch bounce and possible solutions. Apr 13 Preliminary Design Report Due before 5:00 pm Apr 14 No Class. Easter Recess Apr 17 No Class. Easter Recess 33 Apr 19 Decoding counter outputs, glitch-free solution, ring counters 34 Apr 21 Self-correcting ring-counters, Johnson Counters, self-correcting Johnson-counters Homework # 18 assigned for Monday . . . . . . . . . 40 May 5 Last Class Final Project Report Due If you do not have it ready by class time, you need to put it in my hands sometime Friday. May 10 Final exam -- 9 am -- Crothers 351 (Wednesday, May 10th)