Announcements

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@ieee.org
Phone	Office 688-4016; Home number handed out in class
Office	215 Harding Hall
Class Time	MWF 2:00-2:50
Lab Time	The lab will be reserved for this class on Mondays from 3:00-6:50
Class Location	Harding Hall, room 326
Office hours	MWF 11-12, Th 1-2
Textbook	Computer Organization, fifth edition by Carl Hamacher, Zvonko Vranesic, and Safwat Zaky, published by McGraw Hill. For brevity, I will refer to this as HVZ
Reference	Some subset of the following books would prove a valuable reference. Do not buy any of these before speaking w/ Dr. Fourney. Digital Design: Principles & Practices 4th Ed. by John F. Wakerly, published by Prentice Hall (W4e) You will want to refer back to this book if you used if for Digital Design. If you used an earlier edition you should note that the fourth edition also serves as a Verilog reference. The earlier editions are actually better and more complete as digital references, since Prentice Hall put some material on a (poorly thought out, poorly implemented, insecure, subscription based) website in order to make room for the Verilog. So, if you already have access to this book that's a good thing, but if you need to go buy a reference this is not the one to buy. Since most of you do already own this book, I will reference relevant sections and refer to is as W4e. If you own an earlier edition, the stuff I refer to will probably be in your book somewhere, see me if you have trouble finding it. If you don't have access to W4e, you can probably find sufficient Verilog info on the web, but if you feel you need to buy another textbook you could look into: Starters Guide to Verilog 2001, by Michael D. Ciletti (also by Prentice Hall). This is a good Verilog reference, which assumes you already understand digital design. or Digital Logic with Verilog Design, by Stephen Brown and Zvonko Vranesic. This is an excellent textbook which we have adopted for our 245 class. It combines digital design and Verilog in the same text, and you actually buy all of the content instead of renting it via a web site.

Corequisites

The "hands on" portion of this class, EE 492 Section 03, is a required co-requisite. You must be enrolled in both classes.

Course Description

This course serves as an introduction to computer organization. We basically fill in the gaps between your digital systems class (EE 245) and your microcontroller class (EE 347). We show you how to take what you learned in 245 and design the systems you used in 347. We'll discuss various design trade-offs, optimizations, and enhancements to computer designs. After successfully completing this course, the students will be capable of understanding, designing, and building simple computers and will be cognizant of the current trends and design techniques in this area.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will probably be determined via the following breakdown:

 

Exam #1	15%
Exam #2	15%
Homework and Quizzes	15%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Projects & reports	25%
Comprehensive Final Exam	15%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.

Schedule of Upcoming Classes

No. Date Topic, Reading, and Assignment 1 Jan 17 Introduction to Computer Organization (what to expect), go over grading scheme, discuss logistics, schedule lab, show of new Altera based boards. Read Chapter 1 in HVZ 2 Jan 19 Introduction or Rapid Review of Verilog. Before Monday read Sections 5-5.1 and 5.4 of W4e, or Verilog Tutorial, or equivalent. Note that this tutorial doesn't follow the active level signal naming convention that we've used in the past. Let's get in the habit of appending an "_L" to signal names which are active low. The Verilog compiler doesn't care, but it makes it much easier for somebody else to follow your code. For example, using this convention we would name an active low reset signal reset_L 3 Jan 22 Verilog for sequential circuits and finite state machines, continued introduction to Computer Organization (discuss Chapter 1 in HVZ) Lab 1 Jan 22 You should install the DE2 software, and work through the tutorials that came with the boards. PDF versions of the tutorials are here for reference, but Altera has integrated them nicely so that it is easy to use the version that comes with the software while running the actual software. You should install the web edition of the Quartus II software at home, it can be downloaded here. Since you (will) have the software at home, concentrate on the portions of the tutorial that involve downloading and playing with the actual board. 4 Jan 24 Complete discussion of performance equations, cache, superscalar, and history in Chapter 1 of HVZ) 5 Jan 26 Chapter 2 of HVZ. Much of this is review of 245/347 so we will move fairly quickly. 6 Jan 29 Section 2.12 Encoding Machine Instructions, Sections 7-7.3 Basic Processing Unit Lab 2 Jan 29 As either a review or introduction to finite-state machines and Verilog, consult this lab from a digital design course using the Altera boards. (Students currently taking EE 245 at SDSU will be doing a similar lab towards the end of the semester). We will do parts 2, 4, 5, 6, and 7 in order to either get caught up or to review our digital design class and Verilog. You will need to read and understand part 1 (or at least the state diagram) in order to complete part 2. You should also make sure that you would feel comfortable doing parts 1 and 3. If you feel that you don't know how to do these parts, you should see Dr. Fourney in order to review the FSM aspects of EE 245/345. 7 Jan 31 Design of Basic Processing Unit, Algorithmic State Machine (ASM) diagrams. Chapter 7-7.4, and material not in your book Homework assigned for Friday 8 Feb 2 Discuss Homework Due today Discuss lab and brainstorm implementation of our simple machine. Lab 3 prelab. 9 Feb 5 Discuss (new) lab, revert to original assignment Lab 3 Feb 5 Lab 3 10 Feb 7 hardwired vs micro-programmed control, finish chapter 7 11 Feb 9 ARM organization and instruction set 12 Feb 12 Motorola 68000 organization and instruction set Lab 4 Feb 12 Lab 4 13 Feb 14 Intel IA-32 organization and instruction set 14 Feb 16 Memory technology, memory management, cache (Chapter 7) Homework assigned. Demo on Wednesday. Feb 19 No Class/Lab -- President's Day Holiday 15 Feb 21 Cache, virtual memory, memory hierarchy (Chapter 5-5.5) Demo homework after class 16 Feb 23 Cache memory, examples of different mapping strategies, examples of commercial caches. Read through 5.6. Homework assigned. 17 Feb 26 Cache memory details 18 Feb 28 More on Cache and Virtual memory Mar 2 Classes Cancelled due to Snowy Weather Mar 5 No Class/Lab -- Spring Break Mar 7 No Class -- Spring Break Mar 9 No Class -- Spring Break 19 Mar 12 Interrupts and I/O Lab 5 Mar 12 Lab 5 20 Mar 14 Discuss Cache Homework Pi Day 21 Mar 16 Operating System -- Background and Hardware Support 22 Mar 19 Discuss ASM Homework Continue w/ Operating System Support Lab 6 Mar 19 Lab Practical Exam 23 Mar 21 DMA 24 Mar 23 Exam Open book, open notes, bring any handouts I gave you. 25 Mar 26 Pipelining Concepts (Chapter 8) lab 7 Mar 26 Lab 7 26 Mar 28 Go over/discuss Exam Mar 30 Class Cancelled, IEEE Industry Tour 27 Apr 2 Clarify some pipeline concepts, discuss hardware prior to lab lab 8 Apr 2 Lab 8 28 Apr 4 Discuss "typical" pipeline problems culled from the internet. These problems probably came from a class with more of a software interest, but they are good problems and we should understand them. They make decent test problems... Apr 6 No Class -- Easter Recess Apr 9 No Class/Lab -- Easter Recess 29 Apr 11 Organization improvements vs CPU speeds 30 Apr 11 Meet in Lab to work on Pipelined Processor . . . . . . . . . May 8 Final exam -- 2 pm -- Harding 326 (Tuesday, May 8th)