Announcements

1. Final Project 2 reports are now due on Monday, May 5th instead of Friday, May 2nd.

2. Several other changes, including an extra credit assignment, are discussed below in the space for April 28th.

Instructor	Dr. Robert S. Fourney
Email	Robert.Fourney@ieee.org
Phone	Office 688-4016; Home number handed out in class
Office	215 Harding Hall
Class Time	MWF 11:00-11:50
Class Location	Crothers Hall, room 351
Office hours	TBD, with your input, during the first full week of class
Text	Fundamentals of Digital Logic with Verilog Design, 2nd Edition by Stephen Brown and Zvonko Vranesic. Published by McGraw Hill The text will be supplemented with additional reference materials which will be linked from this page and/or handed out in class as they are assigned.

Corequisites

EE 245L -- Digital Systems Lab and either CsC 218 or CsC 150

Course Description

This course serves as an introduction digital logic systems. After successfully completing this course, the students will be capable of understanding, designing, and building both combinational and sequential digital systems.

Course Work

Unless otherwise specified, all work that you submit in this course must be your own; unauthorized collaboration is considered academic dishonesty. Please save us both a lot of trouble by realizing that I will pursue any such transgressions to the fullest extent possible. As a rule, late assigments are not generally accepted (e.g., attempting to hand in an assigment after the start of class on the due date will result in a grade of 0 for that assignment). Late assignments will only be accepted under exceptional circumstances AND with prior arrangement. A penalty may apply.

Grading Policy

Final grades will be determined using the following breakdown:

 

Exam #1	20%
Exam #2	20%
Homework and Quizzes	10%
Class Participation (and quizzes)	5%
Design Lab Practical(s)	10%
Lab Project(s) and Report(s)	20%
Comprehensive Final Exam	15%

Your class participation grade will be determined by your on time attendance to class as well as your participation in classroom discussions. Pop quizzes, when given, will cover material previously covered in class, previous homework assignments, and/or simple questions on the current days reading assignment.   Students are required to make a "good faith effort" on all assignments. Failure to do so will adversely effect the grade beyond the limits listed above. You must earn a grade of C or better in EE 245L this semester in order to pass this class Please read Making the Grade by Kurt Wiesenfeld and keep his views (which I share) in mind when deciding how much effort to invest in your coursework.

Schedule of Upcoming Classes

No. Date Topic, Reading, and Assignment 1 Jan 18 Introduction, go over Syllabus Skim Chapter 1, Design Concepts, and Read Chapter 2 through Section 2.3 - Variables and functions, inversion, and Truth Tables Homework # 0 assigned. Jan 21 No Class -- MLK Day Holiday 2 Jan 23 Read Sections 2.3-2.8 -- Truth Tables, Logic Gates and Networks, and Boolean Algebra, and various circuit implementations. Read 3-3.3, 3.5, and skim 3.8-3.8.4 in order to understand the figures in 3.8-3.8.4 Homework # 1 assigned, Due Wednesday January 30th 3 Jan 25 Some practical aspects, NMOS and PMOS transistors (as switches), NMOS and CMOS circuits Minterms, Maxterms, more on duality. SOP and POS implementations. 4 Jan 28 More on Sections 2.3-2.8 -- Truth Tables, Logic Gates and Networks, and Boolean Algebra, and various circuit implementations. Make sure you understand 3-3.3, 3.5, and figures in 3.8-3.8.4 prior to lab tomorrow 5 Jan 30 Karnough Maps, incompletely specified functions Read through Section 4.4 Homework # 2 assigned, Due Monday February 4 Homework #1 Due before class 6 Feb 1 Some MSI components: multiplexers Section 2.8.2 (you have already skimmed this) Transistor switches -- simple approximation Read Section 3.1, memorize Figure 3.4 (also previously assigned) Buffers and three-state buffers from the heading on page 135 to the top of page 138 Transmission gates Section 3.9 more on multiplexers Section 6.1-6.1.1, skipping example 6.2 decoders Section 6.2 skipping example 6.11 encoders Section 6.3 7 Feb 4 Introduction to CAD tools Read sections 2.9-2.10, skipping 2.10.2 Homework 2 due, prior to the start of class 8 Feb 6 Verilog --Read sections 2.9-2.10, skipping 2.10.2 Homework # 3 assigned, Due Monday, Feb 11 9 Feb 8 Number Representation, Addition, Signed numbers, Subtraction Read Chapter 5 through Section 5.3, skipping 5.2.3 and browsing/skimming 5.3.4 only to the extent that it helps you to understand the rest of 5.3) 10 Feb 11 Finish discussing overflow, Signed numbers, Subtraction (Read 5.3.4 only to the extent that it helps you understand the rest, but you will not be tested on this section. Read all of the rest of 5.3), Then start Chapter 7 on sequential circuits (latches) (read through at least Section 7.4) Homework 3 Due Homework # 4 assigned. Due Friday 11 Feb 13 Chapter 7 (through Section 7.7) Edge triggered memory elements(flip flops) 12 Feb 15 Finish discussing edge triggered memory elements(flip flops), completing through Section 7.7 We will come back to Chapter 7 later, but we will first touch on Finite State Machines (in Chapter 8) Homework # 5 assigned, due Wednesday. Homework 4 due prior to the start of class. Feb 18 No Class -- President's Day Holiday 13 Feb 20 Finite State Machines -- analysis, Chapter 8. Read through Section 8.3 and 8.9 prior to class. Homework 5 due prior to the start of class. 14 Feb 22 Finite State Machines -- design You should read Section 8.7 in your text Homework # 7 assigned, due on Monday Project 1 assigned first deliverable due on Friday February 29. Homework 6 due prior to the start of class. 15 Feb 25 More on logic optimization and minimization. Review Section 4.1, especially pages 175-176. Read 4.9 Feb 25 Optional Evening Review Session in CEH 351 at 7 pm Bring questions, this is not a lecture. 16 Feb 27 Exam #1 17 Feb 29 Finish Quine-McClusky example. More on Finite State Machines. State Minimization: Section 8.6 More on the Verilog HDL: Behavior Verilog, syntax, operators. This material is covered in Appendix A in addition to Sections 4.12 and 6.6. 18 Mar 3 More on Verilog. Section 6.6 and Appendix A 19 Mar 5 Still more on Verilog. Section 6.6 and Appendix A Mar 7 No Class. IEEE Industry Tour 20 Mar 10 Sequential Verilog, Chapter 7 examples, shift registers and counters Homework # 8 assigned. Hand in with the results from tomorrow's lab. 21 Mar 12 Counters, ring counters, Johnson counters. Begin to discuss general FSMs in Verilog. Homework # 9 assigned for Friday. 22 Pi Day Some more on ring counters and Johnson counters. Homework # 10 assigned for Wednesday March 26th. Finish with general FSM implementation in Verilog. More information on switch bounce that you may want to consider prior to finishing your pre-lab. Homework 9 and project reports due Have a fun and safe spring break Mar 17 No Class -- St. Patricks day Mar 19 No Class -- Spring Break Mar 21 No Class -- Spring Break Mar 24 No Class -- Easter Monday 23 Mar 26 Programmable Logic Devices (Section 3.6) BCD to seven-segment decoders (Section 6.4) Homework # 11 assigned for Monday. Homework 10 due . . . . . . . . . 26 Apr 2 More timing and clock issues. Homework # 12 assigned for Monday. Also, please read this before class on Monday. Apr 2 Optional evening review session starting at 5 pm in Crothers 324 As usual, you should bring questions as I do not intend to lecture. 27 Apr 4 Exam II 28 Apr 7 Multiplication (Section 5.6) and IEEE floating point notation (Section 5.7-5.7.2 29 Apr 9 Hand back and discuss Exam II Discuss Algorithmic State Machine (ASM) charts (Section 8.10 and the first paragraph in 10.2.2) Apr 10 Last Day to drop a course with a "W" 30 Apr 11 FSM Design example using state diagrams and transition lists. Homework # 13 assigned for Wednesday (since some people were absent due to the confusion over the uncanceled classes), and Project 2 assigned You should be prepared to work on this in lab on Tuesday April 15th and complete it by Monday, April 28th butyou will have additional homework and lab assignments at the same time. 31 Apr 14 Shift and Add Multiplier, Section 10.2.3 32 Apr 16 Simple Data Path and processor -- Sections 7.14.1 and 7.14.2 33 Apr 18 Enhanced processor, memory in verilog, prelab for Tuesday's lab. 34 Apr 21 Asynchronous State Machines -- Chapter 9 through Section 9.3 and 9.6 35 Apr 23 Asynchronous State Machines and Memory Homework # 14 assigned for Monday Homework # 15 assigned for Tuesday 36 Apr 25 Simple VGA controller -- to be implemented in Lab on Tuesday 37 Apr 28 Examples from Section 9.3 and problem 9.17. Homework # 16 assigned for Wednesday Extra Credit Assignment Due Tuesday Please note that homework 15 (your processor) has been elevated to a minor project. You do not need to write a report for this, but you must demonstrate it to me and be able to explain the operation of the processor. You must also email me your Verilog code, and it must be original code. You should include (as a comment in your Verilog file) that it was written by your lab team (specify by name) and that you did not receive any unauthorized help). This is still due on Tuesday, April 29th. The 20% of your semester grade which is based on projects will now be broken down as follows: Project 1 and report 8% Project 2 and report 8% Project 3: Processor 4% (no report) I will accept the Processor late, but there will be a deduction for each day it is late. You will also not be allowed to work on the Extra Credit assignment until you have completed the projects (including the processor) 38 Apr 30 Read Chapter 11 through 11.6 on Testing for today and Friday . . . . . . . . . May 9 Final exam -- 9 am on Friday, May 9th in Crothers 351