Homework # 13  Due Monday, March 31.



Assume that your receiver is a MC68HC11 with an E clock of exactly
2.0000000MHz, and determine both how fast and how slow the sender
can transmit for the system to still work.  Recall that the "start of
the start" is the fist low bit followed by 2-out-of-3 of samples 3, 5, 
and 7 being low.   Recall that samples 8, 9, and 10 (out of 16) are 
used to determine the data value.  Since this is also 2-out-of-3
voting, you can detect the proper value if only 2 of those samples 
are still within the correct time.  

Since the allowed amount of clock drift will vary with how many bits
are sent after re-synching, work this for both the 10 bit and 11 bit
cases.  (So, you've got 4 total sets of numbers to crunch once you set
up the problem)

The hardest part is probably deciding where to "draw the line" and 
count in order to determine the ratio of received bits to sent bits.
You want this to be as late as possible (e.g. as long after the start
bit as possible).

Hand this in prior to class on Monday.  Include some diagrams showning
me where your numbers come from.