Homework # 16  Due Friday, April 25th.  

For just this assignment, you may place it 
in my mailbox.  I will be at the Engineering Expo for most of the day on Friday and
we will not have class.

Perform both the read-access timing analysis and the write-access timing
analysis when a MC 68HC11 clocked at 3.0 MHz is interfaced to a Hitachi
HM6264A-10 (using the circuit shown in Figure 5.17, page 225 of your text)
Use the assumptions stated in class on 4/14 and 4/16. Namely:



	The 74F373 is a LATCH, not a flip flop.  
	20ns is a MAX rise/fall time, it can be less
	74LS00 and 74LS04 have a 15ns propagation delay (at room
		temp), both rising and falling output
	74F138 decoder has a delay of 8 ns
	The 74F373 LATCH has a latch delay of 11.5 ns
	As far as the memory chip is concerned, the "write" ends with
	the FIRST of CS1 going high, CS2 going low or WE going high.


This is basically a "do over" of homework 15 and the analysis we've
done in class.  Don't just substitute the new parameter values into 
the solution we discussed in class on Monday.  Instead, make sure 
that you really understand, and can do this on your own.  

You will have a chance to show this on the final exam.