Homework # 8, initially due Monday, March 16th.

Now due on Wednesday, March 18th


Show how you would use  the PAL-like device from your handout to implement a 
seven-segment decoder (reference, Section 6.4 in your text and your class notes 
from today).

Do this subject to the following constraints:

	A logic value of zero turns the segment on
        Use I4-I1 as the 4 inputs (I4 MSb), and IO2-IO7 and O8  as outputs
	"a" through "g" respectively.  It is VERY important to use the 
	specified pins for the specified functions.
        You need to display all of the possible hex input combinations
		(0-F).
	Add "tails" to your 6 and 9 (the better to distinguish "6" from "b").


Look over the PAL layout FIRST, then start the design process.  Decide, if 
you actually need K-maps, whether you wil want to group 1's or 0's in your 
maps (outputs are AND-OR-Invert and "0" turns a segment on--think about it)
Note that you'll need  different function (e.g. possibly a K-map) for EACH 
of the seven outputs. 

Hand in the work in addition to the marked up copy of the PAL diagram


   _   
  |_           |_
  |_|          |_|    example of "tail" vs "no tail" on 6

   

As discussed in class, you will have 7 truth tables, each having 16 rows.  I 
would draw this as a single table, having 16 rows and a column for each of the
outputs a-g.  Each of these columns is then a single output of your PAL.  You
may or may not need to minimize these functions.  Since the  OR-array of the 
PAL is fixed, you get no extra-credit for using less product terms (you can't
save them for use elsewhere).

Also, for an upcoming lab you will be asked to implement a BCD to seven-segment
decoder, so you should save your design notes from this homework.