Homework # 9, due Wednesday, March 18th.


Refer to Figure 4.29 in your text:

1. Assume that this circuit is constructed using chips from the 74LS family.
Note that a two input OR gate is a 74LS32, and a two input and gate is a
74LS08.  Assume that X1 = 0, X2=1, X3 = 1, X4 = 1, X5 = 0, X6 = 0 and
X7= 0.

Calculate the expected delay from the time X6 changes from 0 to 1 until
the corresponding output appears at "f"

2.  Then calculate the delay from the time X6 changes from 1 back to 0 until
the corresponding change shows up on f.

3. Determine the "single worst case timing delay" for a change in X6

4.  Repeat 1 through 3  for the 74AHCT family, 


Now refer to Figure 7.85 in your text. 

5.  Determine the maximum clock frequency (minimum clock period) that can
be used to clock the circuit in Figure 7.85 in your text.  Consider 
the case where they components are of the 74LS family (74LS74 flip-flops,
74LS86 X-or gates (use the three-level numbers from your chart), 74LS08 
and gates and use the timing parameters from class.  Then round the 
frequency down to a round number (nearest 5 if it is below 10 Hz, nearest 10 
if it above 10 but below 100 HZ, nearest 50 if it is above 100 Hz) and 
calculate the "setup time margin", both as a time and as a percent of the 
minimum required clock period.

6. Repeat # 5 using the 74AHCT family.