Homework 12   Due on Monday, April 20th 


1. Give an ASM Diagram for the FSM in problem 3 of YOUR second 
exam, and give a circuit for realizing this FSM  via a "one hot" 
state assignment.  You should derive your circuit directly from 
the ASM diagram, as discussed in class.

Compare and contrast the two machines (the one you should have 
derived for the test, and the one using the "one hot" assignment.
If you got this wrong on the test you should first correct your 
test circuit in order to have a valid comparison).  Discuss ease 
of design, simplicity of the excitation logic, number of storage 
elements needed and the complexity of the output encoding.

Problems 2 through 4 refer to the arbiter FSM shown in Figure 8.72 
(and/or 8.73) in your text. You are to design this circuit using:

2. A state assignment which minimizes the number of flip-flops, and
3. a "one hot" state assignment.

4. Assume that both of your circuits (from 2 and 3 above)  are to be 
implemented from discrete components, using the 74LSXX family (74LS74 
flip-flops, 74LSXX and-gates, or-gates, whatever).  Calculate the 
delays from the rising clock edge until the "grant" signals are asserted 
for each circuit.  

You might want to refer to Figures 8.76 and 8.77 in your book.

Have a good weekend,