| Week |
Lab Date |
Lab and Background Reading |
| 0 |
Jan 20 |
Labs will not meet today. We don't quite have enough background material to
complete the first lab.
|
| 1 |
Jan 27 |
Lab #1:
Practical Aspects of Digital Circuits,
Boolean Theorems, and Simplification
You should also read
the EE Program
Lab Report Guidelines. Our rules for writing reports will be based off
of this guide, which will be further discussed in your lab sessions.
|
| 2 |
Feb 3 |
Lab #2:
"Don't care" Conditions in Karnough Maps
and a chance to finish the last section of last week's lab...
|
| 3 |
Feb 10 |
Lab #3:
Decoders, Multiplexers, and Design with Structural Verilog
As will be discused in class, mail all pre-lab HDL and all final (after lab)
HDL to
ee245Lsdsu@gmail.com
|
| 4 |
Feb 17 |
Lab #4: Combinational Adders and
Sequential Circuits
When mailing your pre-lab Verilog modules, name them XYZp04add.v,
XYZp04sub.v, and XYZp04dff.v for the adder, subtracter, and D flip-flop
respectively. XYZ should be replaced by your initials.
For example, my adder would be named
RSFp04add.v
Note the "p" for "pre lab".
|
| 5 |
Feb 24 |
Lab #5: More on Verilog,
MSI Components, and Sequential Circuits
|
| 6 |
Mar 3 |
Lab #6: Finite State Machines: Design and Implementation
|
|
Mar 10 |
No Lab -- Spring Break
|
| 7 |
Mar 17 |
No formal lab assignment, and you do not need to attend your own lab session this week. You should
make use of the lab time, and any additional time we can schedule in lab to work
on your project
As a special St. Patty's day treat, we will be holding lab in the new
EECS building. This building is south of Harding Hall, and the new lab
number is EECS 232. Your student ID should open that door, 24/7, starting
about Wednesday.
|
| 8 |
Mar 24 |
Lab #7: Behavioral Verilog and MSI Components
It should be a fairly easy lab to complete.
If you have not already done so,
you will also be asked to
demonstrate your project during your lab session. Only one partner needs to
be present to demo, but any mistakes or messed up explanations will reflect
on both partners.
|
| 8 |
Mar 31 |
Lab #8: Another, more complicated, pop machine
Note that you need to email your Verilog pre-lab in before your lab session
|
| 9 |
Apr 7 |
Practical Exams. Please show up according to
this schedule.
If you start late, we will not be able to give you extra time, so please
be prompt.
|
| 10 |
Apr 14 |
For this week we will perform Part I only of
this lab, and also
Parts I through IV of
this other lab.
These were developed by the author of your
textbook specifically for the DE-2 boards that we are using in lab.
p>First implement a hex to seven-segment decoder (the lab calls
for a BCD to seven-segment decoder, but you have already designed the hex to
seven-segment unit for homework. You will need the hex version for your
project).
Finish with the counter lab
Do not worry about the pre-lab for Part III of the second lab, your TA will show you how to
do this in lab. For Part IV of the second lab, just assume that there is a 50 MHz clock signal
available and your TA will provide any help you need in using the provided clocks. You should
complete the rest of the prelab assignment before coming to lab.
You do not have to write a report for this lab, as much of it will be
incorporated in your final project. You will have some extra time in lab today,
so you should come prepared to work on the switch debouncer we discussed in class.
You will be required to debounce your push-button clock for the final project.
|