Homework # 10  Due Wednesday, March 18th


Complete Problem 5.4 from your text, and the two problems below:

#1  Using a single '138 3-to-8 decoder and as few NAND gates as possible,
Design a memory circuit to fully decode the following address space: 

Unit    size/type    Start Address

U1	2k RAM		$0000
U2	2k RAM		$E000
U3	2k RAM		$4000

and to partially decode:

U4	1K ROM		$8000


(Assume 16 address bits, A15 most significant, etc--as on examples from
book and class notes)

****************************************

#2 Using a single '138 3-to-8 decoder and as few NAND gates as possible,
Design a memory circuit to fully decode the following address space: 

Unit    size/type    Start Address

U1       2k Ram		$6800
U2	 2k RAM		$F000
U3	 2k RAM		$7800

and to partially decode, via a 2-level scheme using an additional 1/2 of
a '139 four 256 byte I/O devices having the following starting addresses:


I/O 0	$6000 
I/O 1	$6100
I/O 2	$6200
I/O 3	$6300


****************************************************************