Homework # 12  

Due on Monday April 6th 




Perform the write-access timing analysis when a MC 68HC11 clocked at 2.0 MHz 
is interfaced to a Hitachi HM6264A-12 (using the circuit shown in Figure 5.17,
page 225 of your text)

Use the assumptions stated in class on Wednesday. Namely:



	The 74F373 is a LATCH, not a flip flop.  
	20ns is a MAX rise/fall time, it can be less
	74LS00 and 74LS00 have a 15ns propagation delay (at room
		temp), both rising and falling output
	74F138 decoder has a delay of 8 ns
	The 74F373 LATCH has a latch delay of 11.5 ns
	As far as the memory chip is concerned, the "write" ends with
	the FIRST of CS1 going high, CS2 going low or WE going high.


What I am looking for is a chart similar to table 5.9 (on page 230
of your text) AND the work you did to calculate these values.  Note that 
your author gives a very detailed explanation of a similar analysis on 
pages 224-233 of your textbook.  You cannot merely copy his values, since
he violates some of the assumptions stated above.  Many of your numbers 
will be the same as his, but some will be different.